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-D_GLIBCXX_DEBUG makes systemc-2.3.0 crash

Hi,   Sorry for posting that here as I guess this is not the usual bug report tool, and also sorry if this is a duplicate. I have tried to look for this issue on the forum, but could not find....

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sc_signal & Operator

Hi,   I want to pass a sc_signal (the reference of one) of any type to a class as a CTOR-argument. Since i found out, that the &-Operator of the class sc_signal<T> is overloaded, so i don't...

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sc_fxnum_observer

Hi,   Can someone show me how to use sc_fxnum_observer class to watch for saturation, roll over etc in objects like sc_fixed?   Thanks, Sam

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How can I derive a SystemC class from another SystemC class?

Is it possible to define a SC class as a derivative of another SC class? For example, a simple D-Flipflop (latch) implementation will have d and clk inputs and a q output. I want to define an...

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Where are code examples from "System Design with SystemC" book?

Can someone please point to where I could find the example code from the book "System Design with SystemC"  by Thorsten Grötker , Stan Liao et al Kluwer, 2002?    This book mentions the example code is...

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Process doesn't get triggered

Hello, I simply don't get why the process axi_run() doesn't get triggered a second time. Here are all relevant(hopefully) code snippets: template<class T, unsigned int BUSWIDTH>...

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SCBuilder SystemC IDE

Hi all, I have written a simple Windows SystemC IDE called SCBuilder.http://www.ht-lab.com/scbuilder.htm The basic idea is to have a dedicated SystemC IDE which allows the user to create...

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SwitchToFiber called on NULL-pointer

Hello! I'm using Visual Studio 2015 to simulate my design. When it reaches a specific size, it throws an exception due to dereferencing a NULL-pointer inside SwitchToFiber. Is there a way to tweak the...

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Skipping this library for "sccom-link"

 Hello Sir,   I am new to the integration of SystemC and UVM components using UVMC library from Mentor. I have compiled the separate library for uvm and uvmc connect library. But with the same target....

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Newbie sc_signal<class T> creation problem

Hi, I'm a newbie with systemc and using it for design. I want to implement a class representing a generic register file which requires a mandatory parameter NUM_REGS in its constructor. I want to then...

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Selling tool written in SystemC 2.2.0

Hi everyone,   During the past years I've developed a very nice simulator in SystemC 2.2.0 and now, since I've some clients interested in using the tool, I would like to sell it.   Basically the idea...

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how to get full hierarchical instance name inside systemc module?

Hi,   In my design I have one module instantiated 3 level down the hierarchy from sc_main. And I want to get the full hierarchical path inside that module as I have to generate different files based on...

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Is dynamic and Static process scheduling differs?

Hi All,   I have below doubts could you please help;   We have two process 1. one with static sensitivity (a,b,c are input ports)   SC_METHOD(P1); sensitivity<<a<<b<<c;   2.second...

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thread

hi,      In systemc is in possible to invoke the same function using multiple threads ? like in c++:   std::thread th1 (print_block,50,); std::thread th2 (print_block,50,);

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error in systemc.h 118:16 error std::gets is not declared using std::gets

hi , I have updated my gcc compiler to 4.9 version . now when I compile my system C model with g++14 compiler option enabled ,it is giving this error in systemC header file systemc.h 118:16 error...

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Runtime warnings

Hello everyone, I've built a little system in SystemC, which compiles without errors. But when I run the simulation, I get (besides a seg fault, which I will debug) the warnings: Warning: (W505) object...

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Compiling SystemC 2.3.1 on Debian 8.5

Hello all,   I just try to install the systemC 2.3.1 library on a debian system (Version 8.5 64 Bit) which is running on a virtual box. The configure process seems to be ok, but I got several errors...

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Error: (E513) an sc_module_name parameter for your constructor is required

Hi all, I have a problem with my assignment. I have "General_Register" class, this class has constructor which will receive arguments: General_Reg(sc_module_name reg_Name_, sc_uint<N>...

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Output of systemC

Hi all, Suppose I have a Module which has 2 processes (SC_CTHREAD) T1, T2, and a shared signal as the follows:   sc_signal<int> a; void T1() {    wait();    while(true) {       a = 1;...

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Memory footprint and unique names for sc_objectS

Hi all,   In the context of a very large hardware design simulated in SystemC, we faced some issues with the large footprint of our simulator. After deep and long memory profiling we identified a...

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How can I control counters within a for loop with a control signal in a...

Hello, I'm writing a module in SystemC which basically works as follows: it receives a string of bytes through a port p_in and a control signal through the port h. The module must save the bytes within...

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Problem to copy a matrix within other one

Hello, I'm coding an SC_THREAD where I receive a flux of pixels which is saved within a buffer called image_buffer. This buffer is of size 3 lines x 720 columns. What I'm trying to do is that when the...

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A question about SC_METHOD and SC_THREAD

Hi all, I am a novice in systemC. When I learn about systemC from examples, I find that SC_MODULE will be used for combination logic and SC_THREAD will be used for sequential logic. Why is it? Can you...

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SC_REPORT_* Confusion

I am a bit confused about the correct usage of the SC_REPORT_* macros.   In "sysc/kernel/sc_simcontext.cpp" we have: SC_REPORT_INFO("/OSCI/SystemC","Simulation stopped by user."); The above is helpful...

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bug in sc_reset::reconcile_resets()

I didn't find an efficient bug report entrance so I decided to post it here to see whether people think this is a bug or not.   I'm trying to use Ralph's solution to reset the sim context (see...

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SystemC clock time period

Hi All,   How to know the time period of clock in design module at ZERO simulation time i.e at end of elaboration  .Is their any API is available to know it ??   Thanks & Regards  Pruthvi Reddy

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how to make my signal accept many writers

Hi,   I have some situations in my models where I have to write a signal from different drivers. To avoid 'multiple drivers to a signal' error I add SC_MANY_WRITERS flag. Is there any way to allow...

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Segmentation fault whe using delayed sc_vector initialization

I am trying to code a very generic module that takes the number of elements of a sc_vector of sc_in from an argument. This module looks like:   transformation_arbiter.h using namespace sc_core; using...

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Processing core design using systemc

Dear all, can any one give me some guidance...I want to design a processing core like any general purpose processor and want it to execute real time program code...like it will have its own instruction...

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Weird SystemC Context

Hi,   I have some models built against SystemC-2.3.1. During simulation, I get an error telling me "in SC_METHODS use next_trigger() instead". I set a breakpoint there, and check cpi->kind. It's...

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Error: (E100) port specified outside of module

Hi all, I have a problem with my project Error: (E100) port specified outside of module: port 'RXDi' (sc_port_base) In file: ..\..\src\sysc\communication\sc_port.cpp:231  this is my codes #include...

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How can I pass definition in command line into sc_main

I have got an error when I was running a test. My bench has been constructed by system C on cadence incisive 14.20.   The run command is like this: irun -sysc -uvmtop "SC:top" -top dut -f list.f...

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why could "sc_signal_resolved" not be resolved (eclipse IDE, ubuntu)

I am new to systemc in ubuntu 14.04 and I am trying to setup up eclipse for a systemc small project. I followed the the provided README in systemc-2.3.1 and the INSTALL to install the library. I then...

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port concatenation during instantiation inside constructor

Hi,   I have three modules A,B and C. I want to integrate these three modules inside TOP module constructor.   Now module A has one port sc_out<<sc_uint<2> > out;        module B has one...

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delay data on sc_in with clock

Hi, I have a module. My module has two port:  sc_in_clk SCKi                                                                     sc_in<sc_bv<12>> RXDi and has a process:...

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Problem with multiport usage

Hi,   I have 2 modules:  one Test Bench (TB) and a Device under Test (DUT). The TB has an output port (p_out) to simulate a power on (bool). The DUT has an input multiport (p_in) and inside the DUT...

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Initialization of nested sc_vector< sc_vector< > >

Hi,   I need a two dimensional array of SystemC-AMS objects. I read that it should be possible to use nested sc_vector to realize a two dimensional grid of SystemC objects. Therefore, I defined it as...

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Get period of sc_clock

Hi, In sc_main function I have a sc_clock and I instance a module A, too. Now inside module A, I want to get period of that sc_clock to delay. Thanks, VanTeo

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SystemC - Splitting the output sampling

Hi, I'm novice to SystemC and CtoS. I'm evaluating the possibility to replace our existing methodology (Verilog) with SystemC and HLS. Unfortunately, the results are terrible for now (we have designs...

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Systemc time based arbiter

Hi, I am trying to write a simple bus-based architecture. But I cant write the arbiter module. There are two processes M1 and M2. The arbiter allocates a different time slot for M1 or M2, so that they...

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SystemC with noexcept (c++11)

Hello All,   I want to understand usage of noexcept with SystemC. I read that using noexcept will provide me performance benefits!   My doubt is how shall I label a member function noexcept, if it is...

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Systemc-2.3.1 Installation problem on Windows 7 with Cygwin

Hello everybody,   I followed the steps below  to install systemc-2.3.1 on Windows 7 (64bits) : I start a cygwin batch and create a objdir directory In this directory I configure the package with...

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how to get the time of the next event

Hi, Is there a function in SystemC which returns the time of the next event? Or if not exists how to implement it? For example I have clock model with 1MHz frequency and I run the model with...

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System C file parsing

I have a header file, a cpp file and a testbench.  Now what i am trying to accomplish is : I have a text file which has a 75 bit packet.  I need to use this packet in an input signal declared in the...

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Getting started

Hello, Here is what I would like to. Design a library of modules. Each module will be implemented in systemc. For this I need the systemc libraries, a text editor and compiler. So easily doable. Next...

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Range of port mapping from outer to inner module input port

Hi,I was trying to map port from a outer module to an input port of inner module. The ports to be mapped in a certain way that a range of input port of outer module is to be mapped with the input port...

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Fifo slots

Hi every one,   My question might be a bit dumb, i'm a bit new to all of this. I have a module using an array of Fifos and I want to initialize em with custom depth (# of slots, not 16 as default)....

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Implicit conversion for sc_bitref and sc_bitref_r in SystemC-2.3.1

With SystemC-2.3.1, the implicit conversion for sc_bitref and sc_bitref_r has changed from sc_logic to bool. Will this be fixed in the next SystemC-2.3.2 release ?   Thanks,

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Usage of Sc_event_or_list

Hello everybody,I try to use an sc_event_or_list object to catch multiple events but I don't know how to identify the event which occurs. the idea is to schedule the transmission of commands at a...

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Take one clock cycle for each thread

Hi, I have 6 thread s1, s2, s3 and I want to that these thread each take one clock cycle. Thread s1 is sensitive at first clock posedge and run in one clock cycle, s2 is sensitive at sencond clock...

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