Hi
When I simulate my SystemC project in Modelsim I get this error:
From what I could ascertain according to the results collected, the logic is correct.
Heres is the code:
Thanks
When I simulate my SystemC project in Modelsim I get this error:
Error: (vsim-6596) Out of bounds: # In process: sc_main/hermes_2d/thread_p_2 @ 872800 ns # ** Fatal: Fatal SystemC error detected, exiting...
From what I could ascertain according to the results collected, the logic is correct.
Heres is the code:
for(int i = 0; i < 16; ++i) { sc_spawn(sc_bind(&hermes_with_pkt_codec_vhd_bfm::sender, this, i)); sc_spawn(sc_bind(&hermes_with_pkt_codec_vhd_bfm::receiver, this, i)); } void receiver(unsigned int agent) { wait(reset); sc_core::sc_lv<16> tx_re_s; sctg::BufferInterface* buffer = _confIf->getBufferIf(agent); tgPacket* packet = 0; if(!buffer) {return;} while(true) { sc_core::wait(clk_ip->posedge_event()); packet = new tgPacket; do { sc_core::wait(clk_ip->posedge_event()); } while(tx_av.read()[agent] == sc_dt::SC_LOGIC_0); packet->address = tx_data.read().range((agent+1)*32-1, agent*32).to_ulong(); do { sc_core::wait(clk_ip->posedge_event()); } while(tx_av.read()[agent] == sc_dt::SC_LOGIC_1); unsigned int tam = tx_data.read().range((agent+1)*32-1, agent*32).to_uint(); for(unsigned int i = 0; i < tam; i++) { do { sc_core::wait(clk_ip->posedge_event()); } while(tx_free.read()[agent] == sc_dt::SC_LOGIC_0); packet->data = new unsigned char[sizeof(unsigned int)]; unsigned int data = tx_data.read().range((agent+1)*32-1, agent*32).to_uint(); *reinterpret_cast<unsigned int*>(packet->data) = data; packet->size += 32/8; do { sc_core::wait(clk_ip->posedge_event()); } while(tx_free.read()[agent] == sc_dt::SC_LOGIC_1); } // Wait until packet fits to agent's buffer while(buffer->rxSpaceLeft() < packet->size) { wait(*(buffer->rxGetReadEvent())); } buffer->rxPutPacket(packet); packet = 0; sc_core::wait(clk_ip->posedge_event()); } }
Thanks