Equivalence of bit duplication from Verilog in SystemC

Hi all, 

I am a user of Verilog all the while, and I am currently looking into raising abstraction level of digital system design. To start off with, I am trying to convert a project written originally in Verilog into SystemC, and then try to synthesize back from SystemC into Verilog to see the synthesis performance.

I am currently stuck with bit duplication in SystemC. For example, in Verilog, we can do bit duplication by using the syntax below:

 output[15:0] = {8{d[8]}, d[7:0]}

I know that SystemC allow for concatenation. However, duplication using 8(d[8]) seem doesn't work in SystemC. Any advice?