Hello,
In system C, A method is called when ever the event in the sensitivity list changes. Like always block in Verilog. Triggering event in sensitive list can be either edge sensitive or level sensitive.
But at the same simulation time, more than one signal in the sensitivity list changes then that method will be triggered more than once, so at the same simulation time the method is executed more no of times, where as in verilog always block after all signals finalized it enters in to the block, how will I overcome this problem in systemC.
Eg: SC_METHOD(writing_to_memory);
sensitive<<data<<address<<rst;
void writing_to_memory()
{
-----
-----
}
In the above example at the simulation time of 100ns, data is changed, and address also changed so the method will be called twice and executed twice..But I don't want this type of bahaviour how will implement..
please help me...
thank you..