Modeling of Timer in Systemc

Hello All,

I need some strong suggestion regarding modeling of TIMER.

I am new in systemc.

Want to know what are the things a best model should consist of and how its modeling should be done ?

Since timer has a clock time period,

should i model it in by incrementing/decrementing the counter and applying a delay for timer period 

or i should model it without any delay by using sensitivity to the new write in register and decremnting/ incrementing the counter value by evaluating the current time period and previous sensitivity time period by clock time period.

With Warm Regards.