Best Practice to Synchronize Modules

Hi,

I created a pair of modules in SystemC. The purpose is to model a data transfer with one side being the source and the other side being the sink. It currently uses SC_THREAD for processing, e.g. (not showing all details):

class Source : sc_module
{
    sc_in<bool> clk;
    sc_in<bool> ready;
    sc_out<bool> valid;
    sc_out<sc_bv<8>> data;

    // This is a SC_THREAD
    void process()
    {
        while(true)
        {
            wait(clk.posedge_event());

            valid.write(data_available());
            wait(SC_ZERO_TIME);

            if (data_available())
            {
                auto datum = get_datum_to_transfer();
                data.write(datum);
                if (ready.read())
                {
                    erase_transferred_datum();
                }
            }
        }
    }

}

class Sink : sc_module
{
    sc_in<bool> clk;
    sc_out<bool> ready;
    sc_in<bool> valid;
    sc_in<sc_bv<8>> data;

    // This is a SC_THREAD
    void process()
    {
        while(true)
        {
            wait(clk.posedge_event());
            
            const bool is_ready = get_ready_state();
            ready.write(is_ready);
            wait(SC_ZERO_TIME);

            if (is_ready && valid.read())
            {
                store_datum(data.read());
            }
        }
    }
}

For testing, the two modules are connected via sc_signal.

Now, the problem that arose was, that it could happen, that ready and valid where assigned at the exact same simulation time respectively on the same rising edge of the clock. Then, the sink could not properly receive the data. I circumvented this by using wait(SC_ZERO_TIME); to issue delta-cycles which fully solved this particular problems.

However, this particular design brings me to the following questions:

1. Assuming, that there are many of these modules in the complete simulation, is the overhead of SC_THREAD negligible? I am aware, that internally pthreads are used and thus the OS has to deal with it (context switches). But I'm wondering, whether this approach will eventually slow the simulation.
2. When implementing the exact same modules with SC_METHOD, is there a possibility to issue delta cycles in order to update the signals, whenever they are written? I found out, that triggering sc_start(SC_ZERO_TIME); results in the same effect. However, I don't think it is appropriate.
3. Is this already the cleanest approach to the given problem of synchronizing two usually independent modules?

Cheers,

Sebastian