Hi
i want to manage the flow of the out put ports of the main controller (see figure)
for this goal i design a counter and connect it to the decoder
the out put of the decoder is T[0] to T[15]
for example the order of the ports as follow
but this idea is not work
ld_dr.write(T.read()[0]); ld_ac.write(T.read()[1]); ld_tr.write(T.read()[2]); ld_ir.write(T.read()[3]); ld_pc.write(T.read()[4]); ld_ar.write(T.read()[5]); ld_ou.write(T.read()[6]); ld_inp.write(T.read()[7]);
the code is here
#include "systemc.h"
// define counter
SC_MODULE(counter) {
sc_in_clk clk;
sc_in <bool> clear;
sc_out <sc_lv <4> > dout;
int countval;
void onetwothree();
SC_CTOR(counter)
{
SC_METHOD(onetwothree);
sensitive<<clk.pos();
}
};
void counter::onetwothree()
{
if (clear)
countval = 0;
else
countval++;
dout = countval;
}
///////////////////////
//define dec
SC_MODULE (dec_4){
sc_in_clk clk;
sc_in< sc_lv<4> > in_d;
sc_out< sc_lv<16> > out_d;
void process() {
if (in_d.read() == "0000")
out_d = "0000000000000001";
else
if (in_d.read() == "0001")
out_d = "0000000000000010";
else
if(in_d.read() =="0010")
out_d = "0000000000000100";
else
if (in_d.read() == "0011")
out_d = "0000000000001000";
else
if (in_d.read() == "0100")
out_d = "0000000000010000";
else
if (in_d.read() == "0101")
out_d = "0000000000100000";
else
if (in_d.read() == "0110")
out_d = "0000000001000000";
else
if (in_d.read() == "0111")
out_d = "0000000010000000";
else
if (in_d.read() == "1000")
out_d = "0000000100000000";
else
if (in_d.read() == "1001")
out_d = "0000001000000000";
else
if(in_d.read() == "1010")
out_d = "0000010000000000";
else
if (in_d.read() == "1011")
out_d = "0000100000000000";
else
if (in_d.read() == "1100")
out_d = "0001000000000000";
else
if (in_d.read() == "1101")
out_d = "0010000000000000";
else
if (in_d.read() == "1110")
out_d = "0100000000000000";
else
if (in_d.read() == "1111")
out_d = "1000000000000000";
}
SC_CTOR(dec_4) {
SC_METHOD(process);
sensitive<<clk.pos();
}
};
//end define module DEC
//define controller
SC_MODULE(controller) {
sc_in_clk clk;
sc_in < sc_lv <16> > T;
sc_out < bool > reset_counter;
sc_out < sc_logic > ld_ac;
sc_out < sc_logic > ld_dr;
sc_out < sc_logic > ld_ir;
sc_out < sc_logic > ld_tr;
sc_out < sc_logic > ld_pc;
sc_out < sc_logic > ld_ar;
sc_out < sc_logic > ld_ou;
sc_out < sc_logic > ld_inp;
void process()
{
ld_dr.write(T.read()[0]);
ld_ac.write(T.read()[1]);
ld_tr.write(T.read()[2]);
ld_ir.write(T.read()[3]);
ld_pc.write(T.read()[4]);
ld_ar.write(T.read()[5]);
ld_ou.write(T.read()[6]);
ld_inp.write(T.read()[7]);
}
SC_CTOR(controller) {
SC_CTHREAD(process,clk.pos());
}
};
///////////////////////////////
// define main_controller madul
SC_MODULE(main_controller) {
sc_in_clk clk;
sc_out < sc_logic > ld_ac;
sc_out < sc_logic > ld_dr;
sc_out < sc_logic > ld_ir;
sc_out < sc_logic > ld_tr;
sc_out < sc_logic > ld_pc;
sc_out < sc_logic > ld_ar;
sc_out < sc_logic > ld_ou;
sc_out < sc_logic > ld_inp;
sc_out <sc_lv <4> > count_out;
sc_out <sc_lv <16> > dec_out;
sc_signal < sc_lv <16> > T;
sc_signal < sc_lv <4> > count2dec;
sc_signal < bool > reset_counter;
dec_4 *DEC_2;
counter *COUNT;
controller *CONTROL;
void copier() {
count_out = count2dec.read();
dec_out = T.read();
}
SC_CTOR(main_controller) {
SC_METHOD(copier);
sensitive << clk;
DEC_2 = new dec_4 ("DEC_2");
DEC_2 -> clk(clk);
DEC_2 -> in_d(count2dec);
DEC_2 -> out_d(T);
COUNT = new counter ("COUNT");
COUNT -> clk(clk);
COUNT -> clear(reset_counter);
COUNT -> dout(count2dec);
CONTROL = new controller ("CONTROL");
CONTROL -> clk(clk);
CONTROL -> T(T);
CONTROL -> reset_counter(reset_counter);
CONTROL -> ld_ac(ld_ac);
CONTROL -> ld_dr(ld_dr);
CONTROL -> ld_ir(ld_ir);
CONTROL -> ld_tr(ld_tr);
CONTROL -> ld_pc(ld_pc);
CONTROL -> ld_ar(ld_ar);
CONTROL -> ld_ou(ld_ou);
CONTROL -> ld_inp(ld_inp);
}
};
SC_MODULE(test_bench) {
sc_in_clk clk;
sc_in < sc_logic > ld_ac;
sc_in < sc_logic > ld_dr;
sc_in < sc_logic > ld_ir;
sc_in < sc_logic > ld_tr;
sc_in < sc_logic > ld_pc;
sc_in < sc_logic > ld_ar;
sc_in < sc_logic > ld_ou;
sc_in < sc_logic > ld_inp;
//sc_in <sc_lv <16> > count_out;
sc_in <sc_lv <4> > count_out;
sc_in <sc_lv <16> > dec_out;
void process()
{
}
SC_CTOR(test_bench) {
SC_CTHREAD(process, clk.pos() );
}
};
int sc_main(int argc, char* argv[]) {
sc_clock clk;
sc_signal < sc_logic > ld_ac;
sc_signal < sc_logic > ld_dr;
sc_signal < sc_logic > ld_ir;
sc_signal < sc_logic > ld_tr;
sc_signal < sc_logic > ld_pc;
sc_signal < sc_logic > ld_ar;
sc_signal < sc_logic > ld_ou;
sc_signal < sc_logic > ld_inp;
//sc_signal < sc_lv <16> > count_out;
sc_signal <sc_lv <4> > count_out;
sc_signal <sc_lv <16> > dec_out;
main_controller *data_p;
test_bench *tb;
data_p = new main_controller("data_p");
data_p->clk(clk);
data_p->ld_ac(ld_ac);
data_p->ld_dr(ld_dr);
data_p->ld_ir(ld_ir);
data_p->ld_tr(ld_tr);
data_p->ld_pc(ld_pc);
data_p->ld_ar(ld_ar);
data_p->ld_ou(ld_ou);
data_p->ld_inp(ld_inp);
//data_p->count_out(count_out);
data_p->count_out(count_out);
data_p->dec_out(dec_out);
tb = new test_bench ("testBench");
tb->clk(clk);
tb->ld_ac(ld_ac);
tb->ld_dr(ld_dr);
tb->ld_ir(ld_ir);
tb->ld_tr(ld_tr);
tb->ld_pc(ld_pc);
tb->ld_ar(ld_ar);
tb->ld_ou(ld_ou);
tb->ld_inp(ld_inp);
// tb->count_out(count_out);
tb->count_out(count_out);
tb->dec_out(dec_out);
sc_trace_file *tf;
tf = sc_create_vcd_trace_file("BufferTraceFile"); // file extension defaults to ".vcd"
sc_trace(tf,clk,"clk");
sc_trace(tf, count_out, "count_out");
sc_trace(tf, dec_out, "dec_out");
sc_trace(tf, ld_ac, "ld_ac");
sc_trace(tf, ld_dr, "ld_dr");
sc_trace(tf, ld_ir, "ld_ir");
sc_trace(tf, ld_tr, "ld_tr");
sc_trace(tf, ld_pc, "ld_pc");
sc_trace(tf, ld_ar, "ld_ar");
sc_trace(tf, ld_ou, "ld_ou");
sc_trace(tf, ld_inp, "ld_inp");
sc_start(50);
sc_close_vcd_trace_file(tf);
return 0;
}
