Output of systemC

Hi all,

Suppose I have a Module which has 2 processes (SC_CTHREAD) T1, T2, and a shared signal as the follows:

sc_signal<int> a;

void T1() {

   wait();

   while(true) {

      a = 1;

      wait();

   }

}

void T2() {

   int b;

   wait();

   while(true) {

      b = a;

      wait();

   }

}

The SystemC design is simulated by 2 clock cycles. Suppose that the execution sequence will be (T1,T2,T1,T2). I donot understand why the ouput is (a = 1, b = 0).

Other execution sequences, like (T1,T2,T2,T1) produce the same output.

I think that the output should be (a=1, b=1).

Thanks,