Problem with multiport usage
Hi, I have 2 modules: one Test Bench (TB) and a Device under Test (DUT). The TB has an output port (p_out) to simulate a power on (bool). The DUT has an input multiport (p_in) and inside the DUT...
View ArticleInitialization of nested sc_vector< sc_vector< > >
Hi, I need a two dimensional array of SystemC-AMS objects. I read that it should be possible to use nested sc_vector to realize a two dimensional grid of SystemC objects. Therefore, I defined it as...
View ArticleGet period of sc_clock
Hi, In sc_main function I have a sc_clock and I instance a module A, too. Now inside module A, I want to get period of that sc_clock to delay. Thanks, VanTeo
View ArticleClik here to view.
SystemC - Splitting the output sampling
Hi, I'm novice to SystemC and CtoS. I'm evaluating the possibility to replace our existing methodology (Verilog) with SystemC and HLS. Unfortunately, the results are terrible for now (we have designs...
View ArticleSystemc time based arbiter
Hi, I am trying to write a simple bus-based architecture. But I cant write the arbiter module. There are two processes M1 and M2. The arbiter allocates a different time slot for M1 or M2, so that they...
View ArticleSystemC with noexcept (c++11)
Hello All, I want to understand usage of noexcept with SystemC. I read that using noexcept will provide me performance benefits! My doubt is how shall I label a member function noexcept, if it is...
View ArticleClik here to view.
Systemc-2.3.1 Installation problem on Windows 7 with Cygwin
Hello everybody, I followed the steps below to install systemc-2.3.1 on Windows 7 (64bits) : I start a cygwin batch and create a objdir directory In this directory I configure the package with...
View Articlehow to get the time of the next event
Hi, Is there a function in SystemC which returns the time of the next event? Or if not exists how to implement it? For example I have clock model with 1MHz frequency and I run the model with...
View ArticleSystem C file parsing
I have a header file, a cpp file and a testbench. Now what i am trying to accomplish is : I have a text file which has a 75 bit packet. I need to use this packet in an input signal declared in the...
View ArticleGetting started
Hello, Here is what I would like to. Design a library of modules. Each module will be implemented in systemc. For this I need the systemc libraries, a text editor and compiler. So easily doable. Next...
View ArticleRange of port mapping from outer to inner module input port
Hi,I was trying to map port from a outer module to an input port of inner module. The ports to be mapped in a certain way that a range of input port of outer module is to be mapped with the input port...
View ArticleClik here to view.
Fifo slots
Hi every one, My question might be a bit dumb, i'm a bit new to all of this. I have a module using an array of Fifos and I want to initialize em with custom depth (# of slots, not 16 as default)....
View ArticleImplicit conversion for sc_bitref and sc_bitref_r in SystemC-2.3.1
With SystemC-2.3.1, the implicit conversion for sc_bitref and sc_bitref_r has changed from sc_logic to bool. Will this be fixed in the next SystemC-2.3.2 release ? Thanks,
View ArticleUsage of Sc_event_or_list
Hello everybody,I try to use an sc_event_or_list object to catch multiple events but I don't know how to identify the event which occurs. the idea is to schedule the transmission of commands at a...
View ArticleTake one clock cycle for each thread
Hi, I have 6 thread s1, s2, s3 and I want to that these thread each take one clock cycle. Thread s1 is sensitive at first clock posedge and run in one clock cycle, s2 is sensitive at sencond clock...
View Article