hi,

when i try to assign a particular bti in a vector by using the statement ff[i]=o..it is showing error. Could any one pls tell what the mistake is.

.....

 sc_signal<sc_bv<8> > ff;

void func(){

sc_int<size>  i;

if(rst){

hi,

when i try to assign a particular bti in a vector by using the statement ff[i]=o..it is showing error. Could any one pls tell what the mistake is.

.....

 sc_signal<sc_bv<8> > ff;

void func(){

sc_int<size>  i;

if(rst){

Hello,

With the following example, I have a method which is sensitive to an event which is notified(immediately) from end_of_elaboration() function.

This gives Segmentation fault (core dumped).

However if I do func_event.notify(SC_ZERO_TIME); or func_event.notify(1,SC_NS), there is no Segmentation fault

#include "systemc.h"

class TOP : public sc_module

{

  public:

  sc_event func_event;

  SC_HAS_PROCESS(TOP);

  TOP(sc_module_name name) {

    SC_METHOD(method_function);

    sensitive<<func_event;

    dont_initialize();

  }

  void end_of_elaboration(){

      func_event.notify();

  }

  void method_function() {

      std::cout<<"inside f() before wait"<<std::endl;

  }

};

int sc_main(int argc, char* argv[])

{

  TOP top("top");

  sc_start();

  return 0;

}

Please have a look, thanks in advance.

Hello there,

I've been trying to create a vcd file which helps me study the waveform of a 2 by 4 decoder. But, when I try to open the file "decoder.vcd" , it tells me that there is no such file or directory [ on Ubuntu 14.0.4  ].

//File: decoder_top.cpp

#include "driver.h"                                 //module that drives DUT
#include "monitor.h"                              //module that monitors DUT
#include "2_by_4_decoder.h"               //module that contains the info of the ports of DUT

int sc_main(int argc, char* argv[])
{
sc_signal<bool> t_select, t_enable, t_z;

sc_trace_file *wf = sc_create_vcd_trace_file("decoder");
wf->set_time_unit(1, SC_NS);


decoder2by4 dcdr("2by4decoder");
dcdr<<t_enable <<t_select <<t_z;

driver d1("GenerateWaveforms");

d1.d_select(t_select);
d1.d_enable(t_enable);
//d1.d_cin(t_cin);

monitor mo1 ("MonitorWaveforms");
mo1<< t_select << t_enable << t_z;

sc_trace(wf, t_select, "t_select");
sc_trace(wf, t_enable, "t_enable");
sc_trace(wf, t_z, "t_z");


sc_start(100, SC_NS);

sc_stop();

sc_close_vcd_trace_file(wf);


return(0);
}


Please help me solve this issue.

Thanks in advance!

Hello,

the class sc_port offers the function get_interface().

Is there also an option to get the bound channel?

Cheers!

Tim

Hi all,

I have a example with systemC. This example is implement and function. I have tried print results out to the monitor, but it seems to be incorrect ( it seems like the "c" variable updates slower than "a" and "b"  variable). Help me, please! 

#define SC_INCLUDE_DYNAMIC_PROCESSES

#include "systemc"
using namespace sc_core;
using namespace sc_dt;
using namespace std;

#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "Initiator.h"
#include "Memory.h"

/*struct Top : public sc_module
{
  Initiator *initiator;
  Memory    *memory;

  SC_CTOR(Top)
  {
    initiator = new Initiator("initiator");
    memory    = new Memory   ("memory");

    initiator->socket.bind( memory->socket );
  }
};*/


int sc_main(int argc, char* argv[])
{
  Initiator *initiator;
  Memory    *memory;

  initiator = new Initiator("initiator");
  memory    = new Memory   ("memory");

  initiator->socket( memory->socket );

  sc_time t(100, SC_PS);

  sc_signal<bool> a,b,c,d;

  initiator->a(a);
  initiator->b(b);
  initiator->c(c);

  memory->d(d);

  sc_trace_file *wf= sc_create_vcd_trace_file("and2");
  sc_trace(wf, initiator->a, "a");
  sc_trace(wf, initiator->b, "b");
  sc_trace(wf, initiator->c, "c");
  sc_trace(wf, memory->d, "d");

  a.write(0);
  b.write(0);

  sc_start(t);
  a.write(0);
  b.write(1);

  sc_start(t);
  a.write(1);
  b.write(0);

  sc_start(t);
  a.write(1);
  b.write(1);

  sc_start(t);
  a.write(0);
  b.write(0);

  sc_start(t);
  sc_stop();

  sc_close_vcd_trace_file(wf);
  return 0;
}

#define SC_INCLUDE_DYNAMIC_PROCESSES

#include "systemc"
using namespace sc_core;
using namespace sc_dt;
using namespace std;

#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"

struct Initiator: sc_module
{
  tlm_utils::simple_initiator_socket<Initiator> socket;

	sc_in<bool> a,b;
	sc_out<bool> c;

  SC_CTOR(Initiator) : socket("socket")
  {
    SC_THREAD(do_and);
	sensitive << a << b;
  }

  void do_and()
  {
	  while(true)
	  {
		c.write(a.read()&b.read());
		data = 0xFF000000 | (c | 0x00000030);

		tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload;
		sc_time delay = sc_time(10, SC_NS);

		tlm::tlm_command cmd = tlm::TLM_WRITE_COMMAND;

		trans->set_command( cmd );
		trans->set_address(0);
		trans->set_data_ptr( reinterpret_cast<unsigned char*>(&data) );
		trans->set_data_length( 4 );
		trans->set_streaming_width( 4 ); // = data_length to indicate no streaming
		trans->set_byte_enable_ptr( 0 ); // 0 indicates unused
		trans->set_dmi_allowed( false ); // Mandatory initial value
		trans->set_response_status( tlm::TLM_INCOMPLETE_RESPONSE ); // Mandatory initial value

		socket->b_transport( *trans, delay );  // Blocking transport call
      
		 //Initiator obliged to check response status and delay
		if ( trans->is_response_error() )
			SC_REPORT_ERROR("TLM-2", "Response error from b_transport");
		
		cout << " a = " << hex << a << " , b = " << hex << b << " , c = " <<  hex << c << " , data = " << hex << data << " , " << sc_time_stamp() << endl;

		wait();
	  }
  }

  int data;
};

#define SC_INCLUDE_DYNAMIC_PROCESSES

#include "systemc"
using namespace sc_core;
using namespace sc_dt;
using namespace std;

#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"

// Target module representing a simple memory

struct Memory: sc_module
{
	sc_out<bool> d;

	enum { SIZE = 256 };
	int mem[SIZE];

	tlm_utils::simple_target_socket<Memory> socket;

  SC_CTOR(Memory) : socket("socket")
  {
    socket.register_b_transport(this, &Memory::b_transport);
  }

  // TLM-2 blocking transport method
	virtual void b_transport( tlm::tlm_generic_payload& trans, sc_time& delay )
  {
     tlm::tlm_command	cmd = trans.get_command();
     sc_dt::uint64		adr = trans.get_address() / 4;
     unsigned char*		ptr = trans.get_data_ptr();
     unsigned int		len = trans.get_data_length();
     unsigned char*		byt = trans.get_byte_enable_ptr();
     unsigned int		wid = trans.get_streaming_width();

    // Obliged to check address range and check for unsupported features,
    //   i.e. byte enables, streaming, and bursts
    // Can ignore DMI hint and extensions
    // Using the SystemC report handler is an acceptable way of signalling an error

    if (adr >= sc_dt::uint64(SIZE) || byt != 0 || len > 4 || wid < len)
      SC_REPORT_ERROR("TLM-2", "Target does not support given generic payload transaction");

    // Obliged to implement read and write commands
    if ( cmd == tlm::TLM_READ_COMMAND )
      memcpy(ptr, &mem[adr], len);
    else if ( cmd == tlm::TLM_WRITE_COMMAND )
      memcpy(&mem[adr], ptr, len);

	trans.set_response_status( tlm::TLM_OK_RESPONSE );

	if (mem[adr] == 0xFF000030)
	{
		d = false;
	}
	else
	{
		d = true;
	}

	//d = mem[adr];

	cout << " ptr = " << hex << ptr << " , mem[" << adr << "] = "  << mem[adr] << " , d = " << d << " , " << sc_time_stamp() << endl;
	
	}
};

Hello there, 

While trying to run the executable, I get the following message:

Hi All,

I am new to system c and TLM.

Currently i am learning systemc and coding basics,

I want helps from you all.

pls give me some suggestion so that i can start learning properly .

currently i have started coding in eclipse based IDE environment with systemc library.

http://euinovation.blogspot.in/2016/02/systemc-development-of-eclipse-on-linux.html

what tool will be good to start with for system c coding ?

what virtulasation tool should i use for SOC simulation or basic basic module simulation and testing.

Since i am new to this pls suggest any kind of guidelines or suggestion is always welcome.

hi,

 Since iam new to systemc and am trying out new things in order to learn , iam getting lot of doubts, hope someone can help me out!!

 like i verilog where we use case statement for implementing fsm,similarly in  systemc to implement some fsm i hope we use switch statement, so is it possible to switch from one case to another? if so how is it done? 

This is part of the code i wanted to realize:

A follow-up question for

http://forums.accellera.org/topic/5443-vector-declaration/

Why square brakets are not overloaded for sc_signal class?  In case underling datatype allows bit-level access, it seems it would be handy to allow it for signals?

Looks like there is no technical limitation to do this, here is an example:

#include <systemc.h>

template< class T, sc_writer_policy POL = SC_DEFAULT_WRITER_POLICY >
struct my_sc_signal : public sc_signal<T, POL> {
    typedef my_sc_signal<T,POL>          this_type;
    typedef sc_signal<T, POL>            base_type;

    explicit my_sc_signal( const char* name_)  : base_type( name_ ){}

    struct signal_writer_helper {
        signal_writer_helper (this_type &s, size_t i) : sig(s), id(i) {}

        template <typename AT>
        void operator = ( const AT& val_ )
        {
            bool value_changed = !( sig.m_cur_val[id] == val_ );

            sig.m_new_val[id] = val_;
            if( value_changed )
                sig.request_update();
        }

        this_type &sig;
        size_t id;

    };

    signal_writer_helper operator [](size_t i) {
        return signal_writer_helper(*this, i);
    }

};


SC_MODULE(test) {

    static const int BUS_WIDTH = 10;
    my_sc_signal<sc_uint<BUS_WIDTH> > test_sig{"test_sig"};

    SC_CTOR(test) {
        SC_THREAD(master_thread);
        SC_METHOD(slave_method);
        sensitive << test_sig;
    }

    void master_thread() {
        for (int i = 0; i < BUS_WIDTH; ++i) {
            test_sig[i] = 1;
            wait(1, SC_NS);
        }

        for (int i = 0; i < BUS_WIDTH; ++i) {
            test_sig[i] = 1;
            wait(1, SC_NS);
        }

        sc_stop();
    }

    void slave_method() {
        cout << "New signal value is: " << test_sig.read() << endl;
    }

};

int sc_main(int argc, char *argv[]) {

    test test_inst("test_inst");
    sc_start();
    return 0;

}

I don't know how to fix this error, help me please

#define SC_INCLUDE_DYNAMIC_PROCESSES

#include "systemc"
using namespace sc_core;
using namespace sc_dt;
using namespace std;

#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "Initiator.h"
#include "Router.h"
#include "Memory.h"

int sc_main(int argc, char* argv[])
{
  Initiator* initiator;
  Router<4>* router;
  Memory*    memory[4];

  initiator = new Initiator("initiator");
  router    = new Router<4>("router");
    for (int i = 0; i < 4; i++)
    {
      char txt[20];
      sprintf(txt, "memory_%d", i);
      memory[i]   = new Memory(txt);
    }

    // Bind sockets
    initiator->socket.bind( router->target_socket );
    for (int i = 0; i < 4; i++) 
		router->initiator_socket[i]->bind( memory[i]->socket );

	sc_time t(100, SC_PS);

  sc_signal<bool> a,b,c;
  sc_signal<int> d;

  initiator->a(a);
  initiator->b(b);
  initiator->c(c);

  memory[0]->d(d);

  sc_trace_file *wf= sc_create_vcd_trace_file("and2");
  sc_trace(wf, initiator->a, "a");
  sc_trace(wf, initiator->b, "b");
  sc_trace(wf, initiator->c, "c");
  sc_trace(wf, memory[0]->d, "d");

  a.write(0);
  b.write(0);

  sc_start(t);
  a.write(0);
  b.write(1);

  sc_start(t);
  a.write(1);
  b.write(0);

  sc_start(t);
  a.write(1);
  b.write(1);

  sc_start(t);
  a.write(0);
  b.write(0);

  sc_start(t);
  sc_stop();

  sc_close_vcd_trace_file(wf);
  return 0;
}

it's error in this lines

memory[0]->d(d);
sc_trace(wf, memory[0]->d, "d");

I am writing I2C model (as per my requirement) which include master.cpp and slave.cpp. There are 2 signals: SDA and SCL, both are type of sc_inout_resolved in both the files. Connection and Port binding is done perfectly in test bench as well.  I am controlling SDA & SCL in file called master.cpp. While transferring ack from slave to master,  SDA will be controlled by slave.cpp (writes SDA 0). After this again master.cpp should control the SDA line for further transactions. But once controlling on SDA switches to slave.cpp, unable to control SDA again from master.cpp. Writing values(0,1) on SDA is not making any difference. I confirmed this issue using gtkwave. Am I missing anything here? Can anyone tell how to handle sc_inout_resolved between 2 models?.

Hello, 

Is any facelift planned for next SystemC release (2.4 or 3.0)?

I want to share some feedback , from synthesizable SystemC designer prospective. 

Recently I’ve done a lot of synthesizable SystemC coding for HLS (High level synthesis tools). I really enjoy the power of synthesizable stateful threads (SC_THREADS), it helps a lot in converting algorithmic C++ code into RTL.  TLM abstraction of synthesizable bus interfaces works well too.

However, If you look at low level syntax details, SystemC code looks really ugly comparing to Verilog.  Consider a simple example:

module adder (
  input [7:0] a, b,
  output [8:0] res
  );

  assign res = a + b;

endmodule

module adder_test;
  reg [7:0] a, b;
  wire [8:0] res;

  adder adder_isnt(
    .a(a),
    .b(b),
    .res(res)
  );

  initial begin
    a = 11; b = 31;
    #1;
    $display("%d",res);
  end

endmodule

If I rewrite in SystemC it would be:

#include <systemc.h>

SC_MODULE(adder) {

   sc_in<uint8_t>      a, b;
   sc_out<sc_uint<9> > sum;

   SC_CTOR(adder)
   : a{"a"}
   , b{"b"}
   , sum{"sum"}
   {
       SC_METHOD(add_method);
       sensitive << a << b;
   }

   void add_method() {
       sum = a + b;
   }
};

SC_MODULE(adder_test) {

   sc_signal<uint8_t>     a, b;
   sc_signal<sc_uint<9>>  sum;

   adder add_inst;

   SC_CTOR(adder_test)
   : a("a")
   , b("b")
   , sum("sum")
   , add_inst("add_inst")
   {
       add_inst.a(a);
       add_inst.b(b);
       add_inst.sum(sum);

       SC_THREAD(test_thread);
   }

   void test_thread() {
       a = 11; b = 31;
       wait(1, SC_PS);
       cout << sum.read() << endl;
       sc_stop();
   }

};

  adder add_inst;

  : add_inst("add_inst")

add_inst.a(a);
add_inst.b(b);
add_inst.sum(sum);

sc_signal<uint8_t>     a{"a"}, b{"b"};
sc_signal<sc_uint<9>>  sum{"sum"};

#define SC_CTOR(user_module_name)                                           \
  typedef std::function<void(user_module_name& self)> bind_func_t;          \
  typedef user_module_name SC_CURRENT_USER_MODULE;                          \
  user_module_name( ::sc_core::sc_module_name, bind_func_t bindf= 0)        \
  { if (bindf) { bindf(*this); }

#define BIND_INST(module_type) \
  [&](module_type& i)

SC_MODULE(adder) {
      sc_in<uint8_t>       a{"a"}, b{"b"};
      sc_out<sc_uint<9> >  sum{"sum"};

      SC_CTOR(adder) {
           ASSIGN( a|b, sum = a + b; );
      }
};

SC_MODULE(adder_test) {
      sc_signal<uint8_t>     a{"a"}, b{"b"};
      sc_signal<sc_uint<9>>  sum{"sum"};

      adder add_inst{"add_inst", BIND_INST(adder) {
              i.a(a);
              i.b(b);
              i.sum(sum);
          }};

      SC_CTOR(adder_test) {          
          SC_THREAD_LAMBDA(test_thread) {
              a = 11; b = 31;
              wait(1, SC_PS);
              cout << sum.read() << endl;
              sc_stop();
          }
      }
};

Hi

I am facing an issue with sc_port sc_export binding.

My following example compiles fine

class initiator : public sc_module {
    public:
    sc_port<sc_signal_inout_if<bool> > out;
    initiator(sc_module_name name){}
};

class target : public sc_module {
    public:
    sc_port<sc_signal_in_if<bool> > in;
    target(sc_module_name name){}
};

int sc_main(int, char**){
    initiator init("init");
    target targ("targ");
    sc_signal<bool> sig;
    init.out(sig);
    targ.in(sig);
    sc_start();
    return 0;
}

But when I move the channel inside the target, and replace sc_port with sc_export, I have following error

class initiator : public sc_module {
    public:
    sc_port<sc_signal_inout_if<bool> > out;
    initiator(sc_module_name name){}
};

class target : public sc_module {
    public:
    sc_export<sc_signal_in_if<bool> > in;
    sc_signal<bool> sig;
    target(sc_module_name name){in(sig);}
};

int sc_main(int, char**){
    initiator init("init");
    target targ("targ");
    init.out(targ.in);
    sc_start();
    return 0;
}

the error is

error: no match for call to ‘(sc_core::sc_port<sc_core::sc_signal_inout_if<bool>, 1, (sc_core::sc_port_policy)0u>) (sc_core::sc_export<sc_core::sc_signal_in_if<bool> >&)’
 

Can you help me in inderstanding this issue ?

Thanks

Rahul

Hello there, 

The simulation for my module stops at 55 ns. This might probably happen because of my driver. In GTKwave , am not able to view what is the input and output at 55(th) ns, since the simulation stops exactly stops at 55. 

How to keep the simulation time to be infinite or extend more so that I can also view the last set of inputs? 

I also tried deactivating the "sc_stop()" command, but no change was found. If so, what's the need of sc_stop() ?

Any help would be appreciated.

Thanks in advance.

Hello

In the following example I am tying to connect the unconnected port to dummy channel in before_end_of_elaboration callback. But it gives me seg fault

#include "systemc.h"

class test : public sc_module {
    public:
    sc_in<bool> in1;
    SC_HAS_PROCESS(test);
    test(sc_module_name name){
        SC_THREAD(fun);
    }

    void fun(){
    }

    void before_end_of_elaboration(){
        sc_signal<bool> sig;
        in1.bind(sig);
    }
};

int sc_main(int, char**){
    test t("t");
    sc_start();
    return 0;
}

Can you please help.

Also the standard says that @page 122 that the time at which deferred port binding is complete is implementation defined, so where I shoudl check my unconnected ports in the module"

Thanks

RahulJn

Hello

As per standard we can create new sc_port in before_end_of_elaboration callback

In the following example, I am creating a new port in before_end_of_elaboration callback but it is not connected in sc_main.

#include "systemc.h"

class test : public sc_module {
    public:
    SC_HAS_PROCESS(test);
    test(sc_module_name name){
        SC_THREAD(fun);
    }
    void fun(){}
    void before_end_of_elaboration(){
        sc_port<sc_signal_inout_if<bool> > in1;
    }
};

int sc_main(int, char**){
    test t("t");
    sc_start(100,SC_NS);
    sc_stop();
    return 0;
}

But I am not getting unconnected port error.

Thanks

RahulJn

It seems like it makes sense to merge sc_*int and sc_big*int types.

Wide buses are all around in modern systems. For example 64 bytes is common size of cache line. 

I do not see a good reason to keep two types for representing types with user-defined size.

For example in Verilog I have single common type for all cases:

bit [31:0] address;
bit [511:0] data;

But in SystemC I will have to use different types:

sc_uint<32> address;
sc_biguint<512> data;

Specializing sc_uint depending on size will not break compatibility with existing Systemc 2.3 code .

constexpr bool is_biguint(unsigned x) { return x > 64; }

template<int n, bool isbig = is_biguint(n)>
struct sc_uint {};

template<int n>
struct sc_uint <n, true>: public sc_unsigned { };

template<int n>
struct sc_uint <n, false>: public sc_uint_base { };