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Are there rollback methods in the engine?

Are there rollback methods in the SystemC engine to rollback the digital state? This is required for the spice co-simulation (in our engine).  

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suspend/resume

Is it possible to suspend and resume the SystemC simulation?

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running sc_run two times

Hi,   int main(int argc, char* argv[]) { int a; a = sc_run(argc, argv); a = sc_run(argc, argv); return a; } I'd like to run sc_run more than one times. Is that possible?  After the second run the a is...

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Installation Problem with SystemC 2.3.0 and Ubuntu 64 bit

Hey,   i use the SystemC 2.3.0 Library on a Ubuntu 64 bit System but it doesn't work. Can someone give me an installation tutorial? A Step-by-Step tutorial with explanations would be nice. The...

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not gate with sc_logic

Hi,   How to implement a simple not gate with sc_logic type inputs? The ! operator is not defined for this type.    

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sc_bool to sc_logic

Hi,   How to convert sc_bool to sc_logic?   I have a clock which is connected to an and gate. The gate accepts sc_logic signals.

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interactive simulation

I'm trying to implement an interactive digital simulator using SystemC. The user can place switches, gates etc. and can simulate the circuit.   I have some problem with switches. Assume there is a...

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sequence of execution for different "start_of_simulation"s

Hi All:   I have some modules which do different operations during "start_of_simulation" period. However, it turns that they are scheduled randomly.(?)   And I would wish that one specified module to...

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virtual platforms, architectural exploration

What is the purpose to make virtual platforms? It just mimics the functionality of hardware? What are things we explore in architectural exploration?

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controlling systemc simulation

Hi,   I have compiled the systemc model to a dll, now I'd like to run the simulation from an another module (.exe) step by step. For example run the simulation to 20ns then run the simulation to 40ns,...

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How to implement i2c clock synchronization using systemc?

Hi,     How to implement i2c clock synchronization using systemc?       /saraswathi

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problem with call C from SystemC

I have a platform for native simulation, composed with sc_main.cpp, native_wrapper.cpp, native_wrapper.h, hardware.... I have to implement another CPU but I didn't find a method to make this. Because...

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ASCII string to sc_bv and vice versa

Hello,   I am somewhat new to SystemC and I am interested in converting ASCII string to sc_bv and vice versa. I tried static casting the string without success.     I am trying with stringstream; first...

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sc_start return on node change

Hi,   I'd like to run sc_start(duration) but to stop when a node change. Nodes are the out ports at top level. Is there this feauture or could you give me guidlines how to implement it?    

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SystemC connect to SystemVerilog Interface?

Hi,   I am interested in wrapping a C model with SystemC wrapper to mimic a future RTL design. Is it possible to create a port that can connect directly to a SystemVerilog Interface? For Example:...

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vhdl after construct

Hi,   What is that in SystemC? a <= b after 10 ns; -- a and b are signals

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SystemC hands-on web-based simulations

Recently I added SystemC support to EDA Playground.   Now it is possible to run SystemC simulations from your web browser (including viewing waves) without installing anything. Here is a SystemC...

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Performance Modeling,Behavioural Modeling,Register Modelling

Hi,   I would like to know what all these terms, what is the difference between each one.

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Why systemC?

Hi,   I have some doubts regarding systemC, please help me      What are the main advantages of systemC compare to the other modelling languages?   why architects choose this language ?   In the...

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last_value of a signal

Hi,   Is there similar in SystemC like last_value attribute in VHDL?   I have a sc_logic signal and I'd like to determine a real negedge (1->0) but not from (X->0). How to do that?  

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