Microsoft Visual Studio Community 2015
Hi, I'm just getting started with SystemC and I'm having trouble getting the examples to work. I have started with simple_bus because it was one of the failing tests under Cygwin64. So I wanted to try...
View ArticleDebugging inside systemc kernel
Hi, I am trying to edit some systemc kernel code to improve the performance of simulation. But I need to be able to debug the code by going through the symbols of each file, so I add --enable_debug...
View ArticleAccellera kernel process order
Hello all, In the standard it's specified that a SystemC implementation "if a specific version of a specific implementation runs a specific application using a specific input data set, the order of...
View ArticleImeediate notification error
Hi all I have a SystemC thread. I create two instances of this thread in main ( so, now two threads are ready to run) What I tired was to randomize the execution order of these two threads, hence...
View Articlesc_port<> binding
Hi all, I created two modules with interfaces as below: M1 : sc_port<sc_fifo_out_if<T>, 0> a M2 : sc_port<sc_fifo_in_if<T>, 0> a2; I have a third module which is also my...
View ArticleMethods and Threads in same module
Hi all I was trying something like: SC_MODULE(A) { sc_out<bool> outP; bool var = false; void procc1() { outP.write(true); var = true; } void procc2() { while(some_condition) { if(var)...
View ArticleHow to disable kernel version output on stderr ?
Hi, I am using the Accellera SystemC kernel and was wondering if there is some API function to disable the version message printed on stderr when the simulation start ? Manu
View Articlevector of vector of SystemC objects
Hi all, I tried without succes to replace a 2D array of sc_signal<bool> by a vector<vector<sc_signal> > After deep investigations I found the sc_vector class. What is the purpose of...
View ArticleProcess at specific point in time
In my SystemC design I would like to execute a process at a particular time provided on the command line by end user. What is the proper way to handle that ? I can think of creating an SC_THREAD and...
View ArticleFuture Work in SystemC
Hi all I did a project in SystemC. I was using SystemC threads and found them to be having a bottleneck due to wait statements due to context switching. So I was just interested to know what are...
View ArticleInter modules communciation
Hi, In my systemc design, I am making high level abstractions about my system. I am not considering at all the time required to transfert information from one module to another. In this case, what...
View ArticleUVM Reporting (SV) of transactions generated from SystemC model
I have an untimed, event driven systemC model inside of a SystemVerilog UVM environment. At time .000150, an actual transaction is detected on the bus, and send to the scoreboard. The transaction...
View ArticleSystemC stack overflow on large system
Hi there, I want to simulate a lager system which calculates the inner product of two large vectors. The target vector size is 10^6, but now I can only achieve 4096. When the size N equals 8192, it...
View ArticleHow to create VCD at different location than the directory from where...
I want to create VCD file at different location than the directory containing executable. Could I pass the intended path of location for VCD file creation into...
View ArticleRetrieve a pointer to an interface of a port
I am trying to get an interface binded with a vector of port declared as sc_vector<sc_in<bool> > : std::vector<sc_object*> children = get_child_objects();sc_signal<bool> *s =...
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Integrating SystemC in MinGW software project
Hi, I'm trying to integrate SystemC into a software project compiling with MinGW/gcc in order to periodically simulate hardware parts . However, linking the software with SystemC libraries (built...
View Articlesc_signal<T>.event() behavior does not match the one described in LRM
SystemC LRM says: 6.4 sc_signal 6.4.9 Member functions for events Member function event shall return the value true if and only if the value of the signal changed in the update phase of the immediately...
View ArticleAccessing simulation time from a custom data type
Hello, I want to create a custom data type which needs to access sc_time_stamp() for some reason. Is there any elegant way to do this ? Regards, Sumit
View ArticleModules with optional (configurable) ports
Hello, I'm working on reusable primitives for synthesizable SystemC (like bus transactors, FIFOs, arithmetic units). Sometimes I need to make some ports optional, for example "number of items" signal...
View ArticleError (E529) at sc_start()
Hi, I'm trying to integrate SystemC into a software project in order to periodically simulate hardware parts. At the entry point of the simulation, I tried a minimalistic example: SC_MODULE(test){...
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