Hi Expers
When I should use notify() and when notify(SC_ZERO_TIME)
Should I always use notify(SC_ZERO_TIME) to overcome threads indeterministics order ?
Is there some scenarion when I should strictly us notify() ?
Is there some scenarion when I should strictly us notify(SC_ZERO_TIME) ?
Thanks
RahulJn
Hi,
I'm fairly new to systemsC and I've a problem with a port binding that I cannot solve. In fact, I cannot understand why it consider a port as not bound. I checked other threads about binding errors, but I dind't find a solution for my case.
the module I created is the following:
SC_MODULE (RF) {
sc_in<sc_uint<32> > datain;
sc_in<sc_uint<4> > fir_instr;
sc_in<bool> clk;
sc_in<bool> reset;
sc_out<sc_uint<32> > q;
and its instance in the main() is as follow:
int sc_main (int argc, char* argv[]) {
sc_signal<bool> clock;
sc_signal<bool> reset;
sc_signal<sc_uint<32> > datain1;
sc_signal<sc_uint<4> > fir_instr;
sc_signal<sc_uint<32> > q;
RF FF("SRF2");
FF.datain(datain1);
FF.fir_instr(fir_instr);
FF.clk(clock);
FF.reset(reset);
FF.q(q);
when I compile the code I get no errors but during the execution I get the following error:
Error: (E112) get interface failed: port is not bound: port 'SRF.port_1' (sc_in)
my understanding is that it doesn't find the binding for "fir_instr" but I don't understand why. Can somebody help me?
Thanks,
Roberto
Hello,
Can I close sc_trace_file dynamically? Can I use sc_close_vcd_trace_file(wf) at any time after sc_trace and sc_create_vcd_trace_file(); I believe so but there is no error in compile time, but it make a Segmentation fault.
//constructor
.
.
SC_THREAD ( vcd_ctrl);
.
.
//
void vcd_ctrl() {
while(1) {
getcmd(command);
if(command=="off") {
sc_close_vcd_trace_file(g_sc_wf);
}
else if(command=="on") {
wf = sc_create_vcd_trace_file("wave");
mod_a->trace();
mod_b->trace();
}
}
}
>>
I studied that, SystemC is useful to know the problems early in the design cycles, like verification, validation, and software development.
But how SystemC is useful in the case of validation and software development, please explain ?
Hello All,
I am wandering for overloading sc_export.
Lets say at the target side I have 3 exports(same transaction type), so how to implement their write functions?
class abc : public sc_module,
public tlm_analysis_if<T>
{
public:
// defining port list
// Analysis Ports
sc_export<tlm::tlm_analysis_if<T > > exp_1;
sc_export<tlm::tlm_analysis_if<T > > exp_2;
//// In the constructor
exp_1(*this);
exp_2(*this);
Declaration:
void write (const T& t){
// What about implement exp_1
}
void write (const T& t){
// What about exp_2 :(
}
Please help me how to overload the write function?
Thanks,
Karandeep
Hi Guys
WIth the below program I was expecting the simulation will be blocked indefinitely but it exits and total simulation time is 0
Can someone tells me why it didn'y gets blocked indefinitely ?
#include "systemc.h"
SC_MODULE(event_trial){
public:
sc_event p1,p2;
SC_CTOR(event_trial) {
SC_THREAD(process1);
SC_THREAD(process2);
}
void process1(){
while(1){
wait(p2);
p1.notify();
}
}
void process2(){
while(1){
wait(p1);
p2.notify();
}
}
};
int sc_main(int , char**){
event_trial et("et");
sc_start();
cout<<"Simulation time : "<<sc_time_stamp().value()<<endl;
}
hello,
I trying to do coverage using gcov and can't reach 100% for line coverage, for example:
Hello,
I have a SystemC program encapsulated into a C++ class allowing to interact with a SystemC model.
In order to easily call that program from a scripting language, I would like to generate a shared-library containing all my SystemC program and the SystemC library.
Is it different from generating a classical C/C++ shared-library?
How can you deal with the sc_main required by the SystemC?
Can you point me to some documentation about that topic, I didn't find anything about it for SystemC on the internet...
Thank you!
Regards!
J-B
In README file of systemc 2.3.0, Windows 7 SP1, Microsoft Visual C++ 2010 (10.0) is listed as "has been well tested".
On the other hand, in src/sysc/packages/boost/config/compiler/visualc.hpp:
Hello!
I am working on a SystemC project which has 2 different modules interacting through ports and channels. Both modules are running SC_THREADS. Now, I am having problems using the wait(sc_time) statement. What I want to do is simply to let the time flow (simulated systemC time) while I am inside one thread, without removing the process from the runnable set and without allowing another thread to resume (which happens if I use wait(sc_time)). I want to stay inside the thread, and I want the thread to "take some time" to execute. i need to to this because I am simulating a ram memory, and I want the memory_thread to take some time to execute, in order to emulate memory access delay. How can I do it?
Hello All,
I need to spawn a large number of threads for my simulation using sc_spwan(). My threads
are very small piece of code. When I have 16384 threads the simulation stops by issuing
the following message in iteration 5504 of the loop invoking sc_spawn():
Error: (E549) uncaught exception: std::bad_alloc
In file: ../../../../src/sysc/kernel/sc_except.cpp:98
I know this happens due to stack size, but I don't know how much memory is used by each
thread.
Q1) Is there a way to get the size of stack for each thread? Is there a method/function
like get_stack_size()?
Q2) How can I use set_stack_size() when invoking sc_spawn()?
Q3) My simulation is run in CygWin under Windows 7 (32-bit). Does 32-bit the OS impose a limitation
to the stack size? In other words, can the problem be fixed using a 64-bit OS?
Thank you so much in advance!
Hello,
To allow setting static sensitivity of dynamically spawned processes to an or'd list of sc_events, I expected to see a method like:
void sc_spawn_options::set_sensitivity(const sc_event_or_list *);
but do not see any such. next_trigger and wait however, do accept a reference to sc_event_or_list, so it appears to be inconsistent? For, dynamic sensitivity can use sc_event_or_list, but not static sensitivity..
I suppose we can't use sc_event_or_list to set the static sensitivity of statically spawned threads either (created using SC_THREAD/SC_METHOD) - but that is not my need.
Further, there doesn't seem to be any way to retrieve the list of sc_event from an sc_event_or_list (as, say, std::vector<sc_event *>). If that was possible, then I could have called the set_sensitivity(const sc_event *) method repeatedly, for all events in the or'd list.
Any help appreciated, thanks.
Hello everybody,
While working on a systemC project, I discovered that probably I have some confused ideas about signals and ports. Let's say I have something like this:
//cell.hpp
SC_MODULE(Cell)
{
sc_in<sc_uint<16> > datain;
sc_in<sc_uint<1> > addr_en;
sc_in<sc_uint<1> > enable;
sc_out<sc_uint<16> > dataout;
SC_CTOR(Cell)
{
SC_THREAD(memory_cell);
sensitive << enable << datain << addr_en;
}
private:
void memory_cell();
};
//cell.cpp
void Cell::memory_cell()
{
unsigned short data_cell=11;
while(true)
{
//wait for some input
wait();
if (enable->read()==1 && addr_en->read()==1)
{
data_cell=datain->read();
}
else
{
if(enable->read()==0 && addr_en->read()==1)
{
dataout->write(data_cell);
}
}
}
}
//test.cpp
SC_MODULE(TestBench)
{
sc_signal<sc_uint<1> > address_en_s;
sc_signal<sc_uint<16> > datain_s;
sc_signal<sc_uint<1> > enable_s;
sc_signal<sc_uint<16> > dataout_s;
Cell cella;
SC_CTOR(TestBench) : cella("cella")
{
// Binding
cella.addr_en(address_en_s);
cella.datain(datain_s);
cella.enable(enable_s);
cella.dataout(dataout_s);
SC_THREAD(stimulus_thread);
}
private:
void stimulus_thread() {
//write a value:
datain_s.write(81);
address_en_s.write(1);
enable_s.write(1);
wait(SC_ZERO_TIME);
//read what we have written:
enable_s.write(0);
address_en_s.write(1);
wait(SC_ZERO_TIME);
cout << "Output value: " << dataout_s.read() << endl;
//let's cycle the memory again:
address_en_s.write(0);
wait(SC_ZERO_TIME);
cout << "Output value: " << dataout_s.read() << endl;
}
};
I've tried running this modules and I've noticed something weird (at least, weird for me): when the stimulus writes a value (81), after the wait(SC_ZERO_TIME) the memory thread finds its datain, enable and address_enable values already updated. This is what I expected to happen. The same happens when the stimulus changes the enable_es value, in order to run another cycle in the memory thread and copy the datacell value into the memory cell dataout port. What I don't understand is why after the memory module writes into its dataout port and goes again to the wait() statement at the beginning of the while loop, the stimulus module still has the old value on its dataout_s channel (0), and not the new value(81), which has just been copied by the memory module. Then, if I run another cycle of the memory loop (for example changing some values on the stimulus channels), the dataout channel finnally updates.
In other words, it looks like that if I write into the stimulus channels and then switch to the memory thread, the memory finds the values updated. But if the memory thread writes into its ports, and then i switch to the stimulus thread, the thread still sees the old values on its channels (binded to the memory ports).
I don't know if I am clear, and I am sure that maybe this is a naive question, but i am a newbie with systemC and I need to understand this thing.
I installed systemc-2.3.1 on Ubuntu 14.04.1. The installation appears to have gone well, "make check" passes all tests. When I try running the pipe example stand-alone I get the error listed below:
ayoub@VBox:~/systemc-2.3.1/examples/sysc/pipe$ make
gcc -g -Wall -pedantic -Wno-long-long -Werror -I. -I.. -I/usr/local/systemc-2.3.1/include -c display.cpp -o display.o
gcc -g -Wall -pedantic -Wno-long-long -Werror -I. -I.. -I/usr/local/systemc-2.3.1/include -c main.cpp -o main.o
gcc -g -Wall -pedantic -Wno-long-long -Werror -I. -I.. -I/usr/local/systemc-2.3.1/include -c numgen.cpp -o numgen.o
gcc -g -Wall -pedantic -Wno-long-long -Werror -I. -I.. -I/usr/local/systemc-2.3.1/include -c stage1.cpp -o stage1.o
gcc -g -Wall -pedantic -Wno-long-long -Werror -I. -I.. -I/usr/local/systemc-2.3.1/include -c stage2.cpp -o stage2.o
gcc -g -Wall -pedantic -Wno-long-long -Werror -I. -I.. -I/usr/local/systemc-2.3.1/include -c stage3.cpp -o stage3.o
gcc -g -Wall -pedantic -Wno-long-long -Werror -L. -L.. -L /usr/local/systemc-2.3.1/lib-linux -Wl,-rpath=/usr/local/systemc-2.3.1/lib-linux -o pipe.x display.o main.o numgen.o stage1.o stage2.o stage3.o -lsystemc -lm 2>&1 | c++filt
/usr/bin/ld: main.o: undefined reference to symbol 'operator new(unsigned int)@@GLIBCXX_3.4'
//usr/lib/i386-linux-gnu/libstdc++.so.6: error adding symbols: DSO missing from command line
collect2: error: ld returned 1 exit status
make: *** [pipe.x] Error 1
ayoub@VBox:~/systemc-2.3.1/examples/sysc/pipe$ uname -a
Linux VBox 3.13.0-34-generic #60-Ubuntu SMP Wed Aug 13 15:49:09 UTC 2014 i686 i686 i686 GNU/Linux
ayoub@VBox:~/systemc-2.3.1/examples/sysc/pipe$ g++ --version
g++ (Ubuntu 4.8.2-19ubuntu1) 4.8.2
Copyright © 2013 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Is this a real problem? Is there a fix out some where? I have seen similar c++ issues posted elswhere but no solutions.
Thanks,
Ayoub
So, I am still working on this memory code, and I am still having troubles...
The memory module has some submodules: a decoder, and a sc_vector containing mem_cell modules. The mem_cell has two input ports: datain, and address_enable. Address_enable is connected to the output port of the decoder, while datain is directly connected to the datain port of the memory upper level module.
According to my design, mem_cell is sensitive to both address_enable and datain. My problem is that this signals have different path lengths: address_enable, receiving its value from the decoder, needs an extra delta-cycle to get updated, compared to the datain signal, which comes directly from the memory port. So, when testing, I get unexpected results. I think there must be a simple and effective way to synchronize everything. Would it be correct to put some "delay modules" along the fastest paths, in order to synchronize? Are there any other soulutions? I think I shouldn't modify the submodules, which are neat and already succesfully tested.
Hi All,
I've been trying to have a memory module initialised in reset state.
I've got something like this:
template< class address_bus, class data_bus, unsigned int depth>
SC_MODULE(sp_memory){
sc_in<bool> clk;
sc_in<bool> nrst;
sc_in<address_bus> addr_i;
sc_in<data_bus> data_i;
sc_in<bool> wr_i;
..
...
void sp_mem_process();
data_bus mem[depth]; // for instance in this case data_bus=sc_uint<32>
..
SC_CTOR {
..
SC_CTHREAD(sp_mem_process, clk.pos());
reset_signal_is(nrst,false);
..
}
};
So, after several trials I ended up with the following best case,which is OK for simulation but still could not be synthesised.
template< class mem_word, unsigned int depth, const char * mem_init_file>
SC_MODULE(sp_memory){
..
};
This means I give content of a init file to each memory module instance, after which the array mem is initialised with the content of the file in a loop in reset state of the process sp_mem_process().
This is not synthesis-able in the tool I'm using and I believe it's not up to the tool?
So, I want to have a synthesis-able memory initialised from a init_file in pre-reset state. What is your experience on this?
I know that the brute force solution is that the memory is initialised externally, by writing to it as soon as it leaves reset state, but this is not compliant with the HW behaviour that normally can be found in, for instance, FPGA block RAM.
Thanks a lot!
Veljko
Hello to everyone,
I would like to ask if it is possible to give a static order for a number of processes in the SystemC Scheduler. Suppose we have 4 processes a,b,c and d. I would like for each clock tick to trigger the processes in the following way:
clock tick=1 a,b,c,a,b,c,a,b,c,d,d,d
clock tick=2 a,b,c,a,b,c,a,b,c,d,d,d
clock tick=3 a,b,c,a,b,c,a,b,c,d,d,d
clock tick=4 a,b,c,a,b,c,a,b,c,d,d,d
....
Thank you in advance
In a SC_METHOD which is triggered by multiple signals in a sensitivity list, is it possible to find out automatically which signal among the list has asserted, i.e without polling for each signal's value ?
Hi,
I have to instantiate a module multiple times. The Sample code is as below:
#define BUS_WIDTH1 32
#define BUS_WIDTH2 16
SC_MODULE( mymod )
{
sc_in<sc_bv<BUS_WIDTH1> > din;
sc_out<sc_bv<BUS_WIDTH2> > dout;
sub_mod s1;
SC_CTOR( mymod ): s1(BUS_WIDTH2)
{
// Port Connections
}
};
SC_MODULE( sub_mod )
{
sc_in<sc_bv<BUS_WIDTH> > in;
.
.
SC_HAS_PROCESS( sub_mod);
sub_mod(sc_module_name nm,int BUS_WIDTH):sc_module(nm)
{
}
};
I am passing a parameter value BUS_WIDTH2 to sub module and the Sub module parameter is used in the port declaration.....
It is not working...
Can any one suggest a way......?
I tried to write and read an unsigned long long value over a double channel, using a double value as starting point.
Code snippet:
double d = 3.1415926535897931;
unsigned long long * ullp = (unsigned long long *) &d;
out_port.write(*ullp); // sc_out<double> out_port; connected via sc_signal<double> to in_port
unsigned long long ull = in_port.read(); // sc_in<double> in_port; connected via sc_signal<double> to out_port
double * dp = (double *) &ull;
When I print the values of d, *ullp, ull and *dp, I notice the following:
d: 3.1415926535897931;
*ullp: 4614256656552045848;
ull: 4614256656552045568;
*dp: 3.1415926535896688;
However, plain casting without SystemC (double d -> ull* ullp = (ull*) &d -> ull u = *ullp -> double* dp = (double*) &u -> double d2 = *dp) returns d2 with exactly the same value as d.
Any idea what is happening and why the channel of type double seems to loose a bit of its precision when using it in this way?
--
greetz,
Bas