hello all ,
i am just started to use sc_process_handler and the suspend/wait usuage is somewhat similar to wait(e) (ignoring its implementation w.r.t schedular) ...
as i see that from the usuage point of view i can replace suspend/resume any where i have wait(e) ...
can anyone tell me the difference here ...
for suspend/resume
#include "systemc.h"
class test : public sc_module {
public :
sc_process_handle t ;
SC_HAS_PROCESS(test);
test(sc_module_name){
SC_THREAD(run);
t = sc_get_current_process_handle();
SC_THREAD(run2);
}
void run(){
wait(10,SC_NS);
cout<<"T :run1 "<<sc_time_stamp().value()<<endl;
wait(5,SC_NS);
cout<<"T :run2 "<<sc_time_stamp().value()<<endl;
}
void run2(){
wait(10,SC_NS);
cout<<"T :run3 "<<sc_time_stamp().value()<<endl;
t.suspend();
//t.disable();
cout<<"T :run4 "<<sc_time_stamp().value()<<endl;
wait(20,SC_NS);
cout<<"T :run5 "<<sc_time_stamp().value()<<endl;
t.resume();
//t.enable();
cout<<"T :run6 "<<sc_time_stamp().value()<<endl;
//t.reset();
}
};
int sc_main(int, char**){
test t("test");
sc_start();
return 0;
}
mic-24@localhost tmp]$ ./run.x
SystemC 2.3.1-Accellera --- May 1 2014 15:38:34
Copyright (c) 1996-2014 by all Contributors,
ALL RIGHTS RESERVED
T :run1 10000
T :run3 10000
T :run4 10000
T :run5 30000
T :run6 30000
T :run2 30000
here i dont understand why final value is 30000 not 35000 and what happenened to this "wait(5,SC_NS);"
now in disable/resume
#include "systemc.h"
class test : public sc_module {
public :
sc_process_handle t ;
SC_HAS_PROCESS(test);
test(sc_module_name){
SC_THREAD(run);
t = sc_get_current_process_handle();
SC_THREAD(run2);
}
void run(){
wait(10,SC_NS);
cout<<"T :run1 "<<sc_time_stamp().value()<<endl;
wait(5,SC_NS);
cout<<"T :run2 "<<sc_time_stamp().value()<<endl;
}
void run2(){
wait(10,SC_NS);
cout<<"T :run3 "<<sc_time_stamp().value()<<endl;
//t.suspend();
t.disable();
cout<<"T :run4 "<<sc_time_stamp().value()<<endl;
wait(20,SC_NS);
cout<<"T :run5 "<<sc_time_stamp().value()<<endl;
//t.resume();
t.enable();
cout<<"T :run6 "<<sc_time_stamp().value()<<endl;
//t.reset();
}
};
int sc_main(int, char**){
test t("test");
sc_start();
return 0;
}
[mic-24@localhost tmp]$ ./run.x
SystemC 2.3.1-Accellera --- May 1 2014 15:38:34
Copyright (c) 1996-2014 by all Contributors,
ALL RIGHTS RESERVED
T :run1 10000
T :run3 10000
Error: (E559) Undefined process control interaction: attempt to disable a thread with timeout wait: test.run
In file: ../../../../src/sysc/kernel/sc_process.cpp:345
In process: test.run2 @ 10 ns
[mic-24@localhost tmp]$
what is the problem here ???
hello,
I want install SystemC 2.3.0 in my Ubuntu 14.04 (64 bit),and enter these below commands:
mkdir objdir -> cd objdir -> export CXX=g++ -> ../configure -> make
when i enter "make" command this error is occured:
/bin/bash: -c: line 1: syntax error: unexpected end of file
make: *** [all-recursive] Error 1
I will be glad if anyone can help me
Hello,
I am trying to use the following structure to set up a set of event queues:
sc_vector<sc_event_queue> event_lists;
and then have the following structure within my module
SC_METHOD(writer); for (int i=1; i <= NMAX; ++i) sensitive << event_lists[i];
to define the sensivity list for my writer method (yes, I know I indexed from 1...index 0 is used in a different method).
With this in mind, some questions:
Is there any way in "writer" to identify which list item (or items) in the sc_vector triggered the execution of the process?
Assuming multiple items in event lists may be triggered to occur in a given delta cycle (e.g, both event_lists[2] and event_lists[5] should trigger the method in cycle t), is this an appropriate method of handling them or would they occur in cycles t and t+1? If not, what is the proper/best approach for handling this?
As a bit of further background, I am essentially trying to create an NxN crossbar network where when a packet arrives on input X, I put an event on the queue (via notify) to write a packet to output Y after some delay. My main goal is to have N be parameterizable as I will want/need to check different values of N.
Thanks,
Tim
while running a systemC program I get an error
Error: <E107> bind interface to port failed: type mismatch on port 4 of module 'communication_interface'
What does this mean?
Difference between these simulators
Hi all.
What are the difference between these simulators (OSU Abakus 1.0 ,OSU SystemC and OSCI SystemC) and how I can download it ?
Thank you.
Hello all,
I am writing some template code which manipulates some SystemC values, and I came across a place where I am having problems deducing the bit-width of an sc_uint. In looking over the source code for sc_uint (and sc_uint_base), I see that while the width must be specified as a template parameter, it is stored in a (non-const) member variable of every instance. I was wondering why the length is implemented this way, and not as a static method which returns the template parameter? I can't find any place where the width can be changed dynamically. If the length were implemented as a reference to the template parameter, template code would be easier to write, and every object would be smaller.
Thanks,
--Mark
Respected Friends and Elders, could anybody tell me from where I can find the complete API documentation of systemc libraries??
hello ,
I have a problem here where i am using wait(e1||e2) now when it comes out of this wait statement i have to perform some functionality
when e1 is triggerred and some functionality when e2 triggered ...
thnaks ...
Dear All,
I created a class BusAssembly, which basically contains a matrix of sc_uint<>, and I provided it with operator= , ==, >> and sc_trace.
In a simple sc_main I defined some variables with type sc_signal<BusAssembly<W,Dim0,Dim1> > . Then I assinged them with a static matrix. (Both by = or .write())
Now, the new_value of the sc_signal variables is correctly assigned, but after a while of simulaiton, their current value is not updated to it. Surprisingly it is only working for the fisrt assignment occurrence.
SystemC 2.3.1-Accellera --- Sep 20 2014 12:00:32
Copyright (c) 1996-2014 by all Contributors,
ALL RIGHTS RESERVED
data1 (5,1,1,1,1,1)
name = signal_0
value = (5,1,1,1,1,1)
new value = (5,5,3,1,2,3)
data2 (1,1,1)
name = signal_1
value = (1,1,1)
new value = (1,64,130)
data1 (5,5,3,1,2,3) <-- After simulation data1 is OK
name = signal_0
value = (5,5,3,1,2,3)
new value = (5,0,0,0,0,0)
data2 (1,1,1) <-- data2 is not
name = signal_1
value = (1,1,1)
new value = (1,0,0)
data1 (5,5,3,1,2,3) <-- data1 is not
name = signal_0
value = (5,5,3,1,2,3)
new value = (5,0,0,0,0,0)
data2 (1,1,1) <-- neither data2
name = signal_1
value = (1,1,1)
new value = (1,0,0)
What am I mistaken with ?
Thank you in advance.
Please find here the sc_main code:
#include <iostream>
#include "frames.h"
using namespace std;
int sc_main(int argc, char *argv[])
{
// Testbench internal variables
static const sc_uint<4> a[5][1] = {{5},{3},{1},{2},{3}};
static const sc_uint<4> b[5][1] = {{0},{0},{0},{0},{0}};
static const sc_uint<8> c[1][2] = {{64,130}};
static const sc_uint<8> d[1][2] = {{0,0}};
sc_signal<BusAssembly<4,5> > data1;
sc_signal<BusAssembly<8,1,2> > data2;
sc_clock clk("clk",10,SC_NS,true);
data1.write(a);
cout << "data1 " << data1 << "\n";
data1.dump();
data2.write(c);
cout << "data2 " << data2 << "\n";
data2.dump();
sc_start(20,SC_NS);
data1 = b;
cout << "data1 " << data1 << "\n";
data1.dump();
data2 = d;
cout << "data2 " << data2 << "\n";
data2.dump();
sc_start(20,SC_NS);
data1.dump();
data2.dump();
return EXIT_SUCCESS;
}
And the Class definition one "frames.h" :
#include <exception>
#include "systemc.h"
#include <stdio.h>
template <int W=8, unsigned short Dim0=1, unsigned short Dim1=1>
class BusAssembly
{
private:
static const unsigned short dim = Dim0;
public:
sc_uint<W> value[Dim0][Dim1];
BusAssembly()
{
for (unsigned short i=0; i<Dim0; i++)
for (unsigned short j=0; j<Dim1; j++)
value[i][j] = 1;
}
BusAssembly(const sc_uint<W> t[][Dim1])
{
for (unsigned short i=0; i<Dim0; i++)
for (unsigned short j=0; j<Dim1; j++)
value[i][j] = t[i][j];
}
// Assignment operator
BusAssembly& operator = (const BusAssembly& v)
{
if (this == &v)
return *this;
if (dim == v.dim)
{
for (unsigned short i=0; i<Dim0; i++)
for (unsigned short j=0; j<Dim1; j++)
value[i][j] = v.value[i][j];
// cout << *this << "\n";
return *this;
}
else
throw "Assignment Error: Dimensions must match!";
}
bool operator == (const BusAssembly& v) const
{
bool end = true;
if (dim == v.dim)
{
for (unsigned short i=0; i<Dim0 && end; i++)
for (unsigned short j=0; j<Dim1 && end; j++)
end = (value[i][j] != v.value[i][j]);
return end;
}
else
throw "Assignment Error: Dimensions must match!";
}
inline friend void sc_trace (sc_trace_file *tf, const BusAssembly& v, const std::string& NAME)
{
// sc_trace(tf,v.dim, NAME + ".dim");
for (unsigned short i=0; i<Dim0; i++)
for (unsigned short j=0; j<Dim1; j++)
{
std::stringstream str;
str << NAME << ".value(" << i << ")(" << j << ")";
sc_trace(tf,v.value[i][j],str.str());
}
}
inline friend ostream& operator << (ostream& os, const BusAssembly& v)
{
os << "(" << v.dim ;
for (unsigned short i=0; i<Dim0; i++)
for (unsigned short j=0; j<Dim1; j++)
os << "," << v.value[i][j];
os << ")";
return os;
}
};
Hi All,
I am starting the practical implementation of systemc code for 4 bit counter using d flip flop. It works properly as it is, But the problem is with the vcd trace file. The main module produces a vcd file of type .vcd format but when i tried to open it in the gtkwave viewer, the vcd file cannot be opened. There is no error message also for debugging the problem.
My systemc code is given below
//dff.cpp
#include <systemc.h>
SC_MODULE (dff) {
sc_in <bool> clk;
sc_in <bool> din;
sc_out <bool> dout,;
void dff_method()
{
dout=din;
}
SC_CTOR (dff) {
SC_METHOD (dff_method);
sensitive_pos << clk;
}
}
//main.cpp
#include <systemc.h>
#include "dff.cpp"
int sc_main(int argc, char* argv[])
{
sc_core::sc_report_handler::set_actions( "/IEEE_Std_1666/deprecated",
sc_core::SC_DO_NOTHING );
sc_set_time_resolution(100, SC_PS);
sc_signal<bool> din1, dout1;
sc_signal<bool> din2, dout2;
sc_signal<bool> din3, dout3;
sc_signal<bool> din4, dout4;
sc_signal<bool> en;
sc_signal<bool> clk;
int i;
dff dff1("dff");
dff1.din(din1);
dff1.dout(dout1);
dff1.clk(clk);
dff dff2("dff");
dff2.din(din2);
dff2.dout(dout2);
dff2.clk(clk);
dff dff3("dff");
dff3.din(din3);
dff3.dout(dout3);
dff3.clk(clk);
dff dff4("dff");
dff4.din(din4);
dff4.dout(dout4);
dff4.clk(clk);
sc_trace_file *fp; // VCD file
fp=sc_create_vcd_trace_file("wave");
sc_trace(fp,clk,"clk"); // signals
sc_trace(fp,din1,"en");
sc_trace(fp,dout1,"dout_one");
sc_trace(fp,dout2,"dout_two");
sc_trace(fp,dout3,"dout_three");
sc_trace(fp,dout4,"dout_four");
en=1;
for(i=0;i<40;i++)
{
din1=en^dout1;
din2=((en&dout1)^dout2);
din3=(((en&dout1)&dout2)^dout3);
din4=((((en&dout1)&dout2)&dout3)^dout4);
clk=0;
sc_start(1, SC_NS);
clk=1;
sc_start(1, SC_NS);
cout<<" @ "<<sc_time_stamp()<<" dout: "<<dout4<<dout3<<dout2<<dout1<<endl;
}
sc_close_vcd_trace_file(fp);
return 0;
}
and the vcd file is shown as below when opened in vi editior:
$date
Oct 13, 2014 21:46:55
$end
$version
SystemC 2.3.1-Accellera --- Oct 8 2014 22:37:31
$end
$timescale
100 ps
$end
$scope module SystemC $end
$var wire 1 aaaaa clk $end
$var wire 1 aaaab en $end
$var wire 1 aaaac dout_one $end
$var wire 1 aaaad dout_two $end
$var wire 1 aaaae dout_three $end
$var wire 1 aaaaf dout_four $end
$upscope $end
$enddefinitions $end
$comment
All initial values are dumped below at time 0 sec = 0 timescale units.
$end
$dumpvars
0aaaaa
0aaaab
0aaaac
0aaaad
0aaaae
0aaaaf
$end
#10
1aaaaa
#20
0aaaaa
1aaaab
#30
1aaaaa
1aaaac
#40
0aaaaa
0aaaab
#50
1aaaaa
0aaaac
1aaaad
#60
0aaaaa
1aaaab
#70
1aaaaa
1aaaac
#80
0aaaaa
0aaaab
#90
1aaaaa
0aaaac
0aaaad
1aaaae
#100
0aaaaa
1aaaab
#110
1aaaaa
1aaaac
#120
0aaaaa
0aaaab
#130
1aaaaa
0aaaac
1aaaad
#140
0aaaaa
1aaaab
#150
1aaaaa
1aaaac
#160
0aaaaa
0aaaab
#170
1aaaaa
0aaaac
0aaaad
0aaaae
1aaaaf
#180
0aaaaa
1aaaab
#190
1aaaaa
1aaaac
#200
0aaaaa
0aaaab
#210
1aaaaa
0aaaac
1aaaad
#220
0aaaaa
1aaaab
#230
1aaaaa
1aaaac
#240
0aaaaa
0aaaab
#250
1aaaaa
0aaaac
0aaaad
1aaaae
#260
0aaaaa
1aaaab
#270
1aaaaa
1aaaac
#280
0aaaaa
0aaaab
#290
1aaaaa
0aaaac
1aaaad
#300
0aaaaa
1aaaab
#310
1aaaaa
1aaaac
#320
0aaaaa
0aaaab
#330
1aaaaa
0aaaac
0aaaad
0aaaae
0aaaaf
#340
0aaaaa
1aaaab
#350
1aaaaa
1aaaac
#360
0aaaaa
0aaaab
#370
1aaaaa
0aaaac
1aaaad
#380
0aaaaa
1aaaab
#390
1aaaaa
1aaaac
#400
0aaaaa
0aaaab
#410
1aaaaa
0aaaac
0aaaad
1aaaae
#420
0aaaaa
1aaaab
#430
1aaaaa
1aaaac
#440
0aaaaa
0aaaab
#450
1aaaaa
0aaaac
1aaaad
#460
0aaaaa
1aaaab
#470
1aaaaa
1aaaac
#480
0aaaaa
0aaaab
#490
1aaaaa
0aaaac
0aaaad
0aaaae
1aaaaf
#500
0aaaaa
1aaaab
#510
1aaaaa
1aaaac
#520
0aaaaa
0aaaab
#530
1aaaaa
0aaaac
1aaaad
#540
0aaaaa
1aaaab
#550
1aaaaa
1aaaac
#560
0aaaaa
0aaaab
#570
1aaaaa
0aaaac
0aaaad
1aaaae
#580
0aaaaa
1aaaab
#590
1aaaaa
1aaaac
#600
0aaaaa
0aaaab
#610
1aaaaa
0aaaac
1aaaad
#620
0aaaaa
1aaaab
#630
1aaaaa
1aaaac
#640
0aaaaa
0aaaab
#650
1aaaaa
0aaaac
0aaaad
0aaaae
0aaaaf
#660
0aaaaa
1aaaab
#670
1aaaaa
1aaaac
#680
0aaaaa
0aaaab
#690
1aaaaa
0aaaac
1aaaad
#700
0aaaaa
1aaaab
#710
1aaaaa
1aaaac
#720
0aaaaa
0aaaab
#730
1aaaaa
0aaaac
0aaaad
1aaaae
#740
0aaaaa
1aaaab
#750
1aaaaa
1aaaac
#760
0aaaaa
0aaaab
#770
1aaaaa
0aaaac
1aaaad
#780
0aaaaa
1aaaab
#790
1aaaaa
1aaaac
As you can see the comment in the tracefile
- $comment
- All initial values are dumped below at time 0 sec = 0 timescale units.
- $end
So is this the reason the vcd file cannot be opened? if yes, what changes do i need to do in the main module to get waveform?
Please help me how to proceed to the problem solution.
Thanks in advance.
Hi,
I am aware that there is a proposed LRM and proof of concept implementation of UVM-SystemC.
However, I cannot find any downloads on Accelera website - is it only available to Accelera Members, or am I missing something?
Thanks,
Steven
Hi,
Do you know where I can find some examples about the sc_report_handler ?
I would like to know the possibilities offered by this class.
Thanks,
Mathieu
Hello,
firstly I would like to tell that I am totally new in SystemC, but have some experience in VHDL (6 months I have been designing and learning in it). Now I have jumped from VHDL to designing in C++ using a SystemC library.
And my question is,
is there any way to convert float number to bitfield or some logical vector which would represent this number?
(I mean some function, or method or smt else).
(My task is to convert float number to Double precision floating point format, and with it do some arithmetical operations).
I have find some suggestions how to do that but none of them actually worked when I tried to build it.
Can you give me some suggestion about how to do that please, or how would you do that? I would be really grateful to anybody who could give me something to catch on.
Hi all,
I'm facing problem in Centos i686 architecture .I'm installed Systemc-2.3.1 according to i686 architecture .It's compiling fine but while running it's giving segmentation Fault (core dumped) .Please tell me solution
Thanks,
Pruthvi
I have a question which probably is quite stupid. I developed a Software in the Loop framework in SytemC. This framework is supposed to call in specific discrete time instants some modules to execute. For instance suppose we have module A and B. Module A has to be executed every 10 ms and Module B every 20 ms. The execution order has to be first A and then B when both modules have to be executed.
I am able to do that by having a coordinator module triggered by a clock of 10 ms. Every module ( module A, B and scheduler) are related with an event. Module A and B they look like this:
while(1){
Wait(ev_mod_i)
{
...
trigger_ev_coordinator
}}
The coordinator which knows the frequency of each module will notify the correct event to trigger the corresponding module. So for instance for t=10ms the coordinator will be triggered by the clock and it will trigger event_mod_A. Then for t=20ms it will trigger event_mod_A, after module A is finished coordinator will trigger event_mod_B. After module B is also finished, the coordinator will wait for the next clock tick e.t.c
Now i would like to insert an AMS model into my system. The desired MoC is continuous TDF. However I can't use statements like event.notify(zerotime) or wait(ev_i) in TDF according to the AMS manual. Moreover TDF modules include a time step by which they are executed. This is something that is not fully desired because i can't find a way to control the TDF modules. Could you please give me any ideas on how I can embed a TDF model into a SystemC framework and at the same time to be able to control when the model has to be executed for a specific clock tick? Probably by doing this I am ruining the whole concept of continuous TDF MoC. If this is right do you have any alternative ideas? Thanks in advance.
Hi All,
A basic C++ question, how can I add a method to the class below so that I can write to individual elements?
sc_signal<class des_struct> xyz,abc;
abc.write(xyz.read()); // works fine
xyz.attrib=4; // Error
class des_struct {
public:
uint16_t reg;
uint16_t attrib;
des_struct() {
reg=0;
attrib=0;
}
des_struct& operator= (const des_struct& rhs) {
reg=rhs.reg;
attrib=rhs.attrib;
return *this;
}
....
};
Thanks.
Hi Guys,
Is there a way to cancel the event which results when we write on a signal.
In the following code every time when I am writing on a signal, I also cancel the event on the next line but still process2 is activated.
Thanks
Rahuljn
#include "systemc.h"
SC_MODULE(event_trial){
public:
sc_signal<bool> sig;
SC_CTOR(event_trial) {
SC_THREAD(process1);
SC_THREAD(process2);
}
void process1(){
for(int i=0;i<3;i++){
wait(5, SC_NS);
sig.write(!sig.read());
cout<<"writing on signal at "<<sc_time_stamp().value()<<"("<<sc_delta_count()<<")\n";
const_cast<sc_event*>(&(sig.default_event()))->cancel();
}
}
void process2(){
for(;
{
wait(sig.default_event());
cout<<"\tevent arrived "<<sc_time_stamp().value()<<"("<<sc_delta_count()<<")\n";
}
}
};
int sc_main(int , char**){
event_trial et("et");
sc_start();
return 0;
}
e1.notify();
know thread 1 leaves control after two loop i.e after two event notify now i want thread2 to also run twice ...
