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SystemC without Signals

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Hi All

 

I tried to implement a simple Task Scheduler in SystemC. It works as follows:

I have three modules "TaskA" , "TaskB" and "CPU". The algorithm works in such a way that the CPU gives full utilization if only one task is present at a time and gives 50% utilization if both the tasks are present. The Arrival times of both the tasks are assigned before the start of the simulation. I was able to implement it with ports and signals, but now i want to measure the performace without ports and signals (i.e) using the C++ and the internal clock of systemc( sc_time_stamp(), sc_start() etc ).

 

Presently, i have the following:

 

class Task : sc_module

{

void taskA()

{

....

bool tskA = true;

if(tskA)

{

eventA.notify(10,SC_NS); // Arrival time of A as a Event

tskA = false

}

else

{

outA= true // So that we get the event after 10ns of simualtion time

}

 

void taskB()

{

.....

bool tskB = true;

if(tskB)

{

eventB.notify(20,SC_NS); // Arrival Time of B as a Event

tskB = false;

}

else

{

outB = true; // To get taskB after 20ns after the start simulation 

}

}

 

SC_CTOR()

{

SC_METHOD(taskA);

SC_METHOD(taskB);

 

sensitive << eventA;

sensitive << eventB;

}

 

 

class CPU: sc_module

{

 

Task A;

Task B;

 

void cpu()

{

 

A.taskA();

B.taskB();

 

if(outA)

{

//Debug statement

 

cout << "A arrives @"<< sc_time_stamp() << endl;

 

some calculation

}

else if (outA && outB)

{

//Debug Statement

 

cout << "B arrives @" << sc_time_stamp() << endl;

 

some calculation}

 

}

}

 

SC_CTOR(CPU) : A("AT"), B("BT")

{

SC_METHOD(cpu);

 

sensitive << eventA;

sensitive << eventB;

}

 

 

But, the problem is the modules gets executed always. To me more precise:

 

What I expect as Output is:

 

A arrives @ 10ns

B arrives @ 20ns

 

 

But, What I am getting now is

 

A arrives @ 10ns

B arrives @ 10ns

A arrives @ 20ns

B arrives @ 20ns

 

I am not able to figure out where I am going wrong, can anyone please give me suggestions/ point out the msitake i am doing here?


sc_event_queue query

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Hello,

 

I am having an SC_THREAD as follows

 

//

//

SC_THREAD(my_proc);

sensitive << event_1;

dont_initialize();
//

//

//

 

void my_proc()

{

  while(1)

   {

    wait(10,SC_NS);

    cout << " Display ok";

    wait(event_1);

   }

}

 

My question is i am having an situation where this event get triggered repetedly in short instance of time, lets say at time t=2 ns it get triggered then SC_THREAD starts, then again it get triggered at t=4ns, but this triggerring of event goes unnoticed.

 

I saw some post and from them i got to know that i cant even use sc_event_queue as i am using wait in my thread.

What can be alternative to implement this logic.

Thanks.

SC_THREADS not starting?

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Hello everyone!

I am new in this forum.

I am doing some SystemC exercises after a long time without using it, and I have a very basic problem. I wrote the following code:

#include <iostream>
#include "systemc.h"

SC_MODULE(stim)
{
  sc_in<bool> Clk;

  void StimGen()
  {
    cout << sc_time_stamp() << "Hello World!\n";
  }
  SC_CTOR(stim)
  {
    SC_METHOD(StimGen);
    sensitive << Clk.pos();
  }
};


int sc_main(int argc, char* argv[])
{
  sc_clock TestClk("clk", 10,SC_NS);

  stim Stim1("Stimulus");
  Stim1.Clk(TestClk);

  sc_start();  

  return 0;

}

When run the program, it terminates without printing "Hello World!" string on output. 

What am I doing wrong?

If  I substitute SC_THREAD with SC_METHOD, the "Hello World!" message is printed.

async reset does not reset singlas assigned in a CTHREAD

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Hello everyone,

 

here's the secenario:

CTHREAD A

THREAD B

CTHREAD C

 

CTHREAD A and CTHREAD C are both triggered by the same clock signal, CTHREAD C has an async reset signal assigned to it.

This reset signal is controlled by THREAD B.

 

1. A starts B via notif(), which means B will start in the current evaluation phase.

2. The scheduling happens to be that C runs before B.

3. C runs and does some signal assignment.

4. B runs and asserts the async reset signal of C.

5. The reset code of C is run.

 

But the singal writes in step C are already applied to the corresponding signals in step 5.

Since C is a CTHREAD I would have expected that the singal update happens at the next rising clock edge, not after one delta cycle.

 

The behavior I want, is to revoke all signal assignments done in step 3. Maybe I'm too much influenced by VHDL. For me this is a clocked process and the singals represent registers. The register load the inputs at the clock edge and not in between.

 

Can someone please tell me how to realize this kind of behavior correctly?

Problem with re-instatiation of modules

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Hi,
 
I'm working on a TL-Model in SystemC. Due to some internal necessarities, it is important to re-instantiate the model before a new simulation. I do not want to re-start the whole program. However, I get the following warning:
 

Warning: (W505) object already exists: ast-sink.processSink. Latter declaration will be renamed to ast-sink.processSink_0
In file: ../../../../src/sysc/kernel/sc_object_manager.cpp:149

 
This obviously comes from re-instantiation, since the instantiated module always uses the same name. However, this does not really makes sense to me, since between instantiations, the destructor is called and therefore, also

sc_module_registry::remove

gets called from which I'd assume, that it removes the module properly. This feels like a SystemC bug to me.

 

Cheers,

Sebastian

Best Practice to Synchronize Modules

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Hi,

 

I created a pair of modules in SystemC. The purpose is to model a data transfer with one side being the source and the other side being the sink. It currently uses SC_THREAD for processing, e.g. (not showing all details):

class Source : sc_module
{
    sc_in<bool> clk;
    sc_in<bool> ready;
    sc_out<bool> valid;
    sc_out<sc_bv<8>> data;

    // This is a SC_THREAD
    void process()
    {
        while(true)
        {
            wait(clk.posedge_event());

            valid.write(data_available());
            wait(SC_ZERO_TIME);

            if (data_available())
            {
                auto datum = get_datum_to_transfer();
                data.write(datum);
                if (ready.read())
                {
                    erase_transferred_datum();
                }
            }
        }
    }

}

class Sink : sc_module
{
    sc_in<bool> clk;
    sc_out<bool> ready;
    sc_in<bool> valid;
    sc_in<sc_bv<8>> data;

    // This is a SC_THREAD
    void process()
    {
        while(true)
        {
            wait(clk.posedge_event());
            
            const bool is_ready = get_ready_state();
            ready.write(is_ready);
            wait(SC_ZERO_TIME);

            if (is_ready && valid.read())
            {
                store_datum(data.read());
            }
        }
    }
}

For testing, the two modules are connected via sc_signal.

 

Now, the problem that arose was, that it could happen, that ready and valid where assigned at the exact same simulation time respectively on the same rising edge of the clock. Then, the sink could not properly receive the data. I circumvented this by using wait(SC_ZERO_TIME); to issue delta-cycles which fully solved this particular problems.

 

However, this particular design brings me to the following questions:

 

  1. Assuming, that there are many of these modules in the complete simulation, is the overhead of SC_THREAD negligible? I am aware, that internally pthreads are used and thus the OS has to deal with it (context switches). But I'm wondering, whether this approach will eventually slow the simulation.
  2. When implementing the exact same modules with SC_METHOD, is there a possibility to issue delta cycles in order to update the signals, whenever they are written? I found out, that triggering sc_start(SC_ZERO_TIME); results in the same effect. However, I don't think it is appropriate.
  3. Is this already the cleanest approach to the given problem of synchronizing two usually independent modules?

 

Cheers,

Sebastian

no match for ‘operator=’ in ‘((sync_fifo*)this)->sync_fifo::wptr = 0’

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Hi All ,

I am new to SytemC  and I am designing a FIFO . When I run the make file I am getting an error " no match for ‘operator=’ in ‘((sync_fifo*)this)->sync_fifo::wptr = 0’ " .  I guess this has do with the sensitivity list  of wptr and rptr but I am not sure how to fix it.I have highlighted the lines where I am getting error . It will be really helpful if someone could explain this .  Thank you :)

 

#include <systemc.h>  

 
SC_MODULE (sync_fifo){
sc_in_clk clk;
sc_in<bool> rst;
sc_in<bool> rd_wr;
sc_out<bool> full;
sc_out<bool> empty;
sc_in < sc_uint<8> > data_in;
sc_in < sc_uint<4> > wptr;
sc_in < sc_uint <4> > rptr;
sc_out < sc_uint<8> > data_out;
 
sc_uint<8> ram_data[256];
 
 
void read_write() {
if(rst == 1)
{
wptr=0;rptr=0;data_out=0;
}
else
if(rd_wr == 1 && !full)
{
ram_data[wptr.read()]=data_in;
wptr=wptr+1;
}
else
if(rd_wr == 0 && !full)
{
data_out=ram_data[rptr.read()];
rptr=rptr+1;
}
}
 
void emp_ful(){
if(rst == 1)
{
full=0;
empty=0;
}
else
{
if(wptr == rptr )
{
empty=1;
}
else if((wptr - rptr) == 15)
{
full=1;
}
    else
{
full=empty=0;
}
}
}
 
 
 
SC_CTOR(sync_fifo)
{
SC_METHOD(read_write);
sensitive << clk.pos() << rst ;
sensitive << wptr ;
sensitive << rptr;
 
SC_METHOD(emp_ful);
sensitive << clk.pos() << rst ;
sensitive << wptr ;
sensitive << rptr ;
}
};
 
 
 
 
 
 
 

Problems with custom Packet Class in sc_in/sc_out

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Hello,

 

I have a Packet class, that for the last week I had to overload some operators ot make it compile using SystemC. Currently I'm trying to instantiate this class in the main file to start testing and I am having compilation issues.

 

The custom class:

 

from my_defines.h

typedef sc_bv< _DATA_SIZE > particle_t;
 

 

#include <systemc.h>
#include "my_defines.h"


class Packet {
public:
    sc_bv< _BITADDR > _field1;
    sc_bv< _BITADDR > _field2;
    sc_bv< _INDEX >     _index;
    particle_t                  _data;

    virtual ~Packet();
    Packet();
    Packet(sc_bv<_BITADDR> _field1, sc_bv< _BITADDR > _field2 sc_bv< _INDEX >     _index, particle_t _data);
   ....
    }
    inline Packet& operator =(const Packet& rhs){
    ...
    }
    inline friend void sc_trace(sc_trace_file *tf, const Packet & v, const std::string & NAME ){
   ....
    }

    inline friend ostream& operator<<(ostream& os,   Packet const & v)
    {
      ....
    }
};

 

 

Queue:

 

SC_MODULE(Queue) {

    sc_in< bool >            rstn;
    sc_in< bool >            clk; // ??? keep it or remove it ?

    //P1
    sc_in< bool >             clkin;
    sc_in< bool >            write;
    sc_in< Packet >            dataIn;
    sc_out< bool >            busyIn;

    //P2
    sc_in< bool >             clkout;
    sc_in< bool >            read;
    sc_out< Packet >        dataOut;
    sc_out< bool >            busyOut; // wait is a reserved word so I used busy for now

//public:


    sc_fifo< Packet > *_buffer;//(_BUFFER_SIZE); //they key component

 

Main file:

...

int sc_main(int argc, char *argv[])
{
    int _channel = 0;


    sc_clock clk("clk",10,SC_NS, 0.5);
    //sc_reset rstn("rstn", 0 , SC_NS, 2.0);

    sc_signal< bool > rstn;// = rstn;

     sc_signal<bool>   enable;
     Packet pkt1,     pkt2;
    pkt1._column = 0x0000;
    pkt1._row      = 0x0001;
    pkt1._flit = 0Xffff;

    Queue tqueue("UUT");

    tqueue.clk(clk);
    tqueue.clkin(clk);
    tqueue.clkout(clk);
    tqueue.rstn(rstn);
    tqueue.dataIn(pkt1);
    tqueue.dataOut(pkt2);
    tqueue.write(true);
    tqueue.read(true);


    sc_start();


    return EXIT_SUCCESS;
}

 

 

Whe I coimpile Queue and Packet it compiles without problems, but when I try to compile the main file I'm receiving the error messages below. I'm using clang++ and the systemc was compiled with clang++ too, so if anyone could give me a help I would appreciate it since SystemC is not exactly 'my cup of tea' and I'm begiinig with it.

 

 

ERROR LOG:

 

clang++     -I. -I.. -I/opt/vlsi/systemc/include  -c src/systemc/packet.cpp -o src/systemc/packet.o
clang++     -I. -I.. -I/opt/vlsi/systemc/include  -c src/systemc/queue.cpp -o src/systemc/queue.o
clang++     -I. -I.. -I/opt/vlsi/systemc/include  -c src/systemc/main.cpp -o src/systemc/main.o
src/systemc/main.cpp:43:2: error: no matching function for call to object of type 'sc_in<Packet>'
        tqueue.dataIn(pkt1);
        ^~~~~~~~~~~~~
/opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:166:10: note: candidate function not viable: no known conversion from 'Packet' to 'const in_if_type' (aka 'const sc_signal_in_if<data_type>') for 1st argument
    void operator () ( const in_if_type& interface_ )
         ^
/opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:175:10: note: candidate function not viable: no known conversion from 'Packet' to 'in_port_type &' (aka 'sc_port<if_type, 1, SC_ONE_OR_MORE_BOUND> &') for 1st argument
    void operator () ( in_port_type& parent_ )
         ^
/opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:184:10: note: candidate function not viable: no known conversion from 'Packet' to 'inout_port_type &' (aka 'sc_port<inout_if_type, 1, SC_ONE_OR_MORE_BOUND> &') for 1st argument
    void operator () ( inout_port_type& parent_ )
         ^
src/systemc/main.cpp:44:2: error: no matching function for call to object of type 'sc_out<Packet>'
        tqueue.dataOut(pkt2);
        ^~~~~~~~~~~~~~
/opt/vlsi/systemc/include/sysc/communication/sc_port.h:270:10: note: candidate function not viable: no known conversion from 'Packet' to 'sc_core::sc_signal_inout_if<Packet> &' for 1st argument
    void operator () ( IF& interface_ )
         ^
/opt/vlsi/systemc/include/sysc/communication/sc_port.h:279:10: note: candidate function not viable: no known conversion from 'Packet' to 'port_type &' (aka 'sc_port_b<sc_core::sc_signal_inout_if<Packet> > &') for 1st argument
    void operator () ( port_type& parent_ )
         ^
src/systemc/main.cpp:45:2: error: no matching function for call to object of type 'sc_in<bool>'
        tqueue.write(true);
        ^~~~~~~~~~~~
/opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:489:10: note: candidate function not viable: no known conversion from 'bool' to 'const in_if_type' (aka 'const sc_signal_in_if<data_type>') for 1st argument
    void operator () ( const in_if_type& interface_ )
         ^
/opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:498:10: note: candidate function not viable: no known conversion from 'bool' to 'in_port_type &' (aka 'sc_port<if_type, 1, SC_ONE_OR_MORE_BOUND> &') for 1st argument
    void operator () ( in_port_type& parent_ )
         ^
/opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:507:10: note: candidate function not viable: no known conversion from 'bool' to 'inout_port_type &' (aka 'sc_port<inout_if_type, 1, SC_ONE_OR_MORE_BOUND> &') for 1st argument
    void operator () ( inout_port_type& parent_ )
         ^
src/systemc/main.cpp:46:2: error: no matching function for call to object of type 'sc_in<bool>'
        tqueue.read(true);
        ^~~~~~~~~~~
/opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:489:10: note: candidate function not viable: no known conversion from 'bool' to 'const in_if_type' (aka 'const sc_signal_in_if<data_type>') for 1st argument
    void operator () ( const in_if_type& interface_ )
         ^
/opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:498:10: note: candidate function not viable: no known conversion from 'bool' to 'in_port_type &' (aka 'sc_port<if_type, 1, SC_ONE_OR_MORE_BOUND> &') for 1st argument
    void operator () ( in_port_type& parent_ )
         ^
/opt/vlsi/systemc/include/sysc/communication/sc_signal_ports.h:507:10: note: candidate function not viable: no known conversion from 'bool' to 'inout_port_type &' (aka 'sc_port<inout_if_type, 1, SC_ONE_OR_MORE_BOUND> &') for 1st argument
    void operator () ( inout_port_type& parent_ )
         ^
4 errors generated.

 


syntax for copying the bit vector , systemC 2.3.1 version

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Hi All ,

I am trying to copy a particular bit  from one bit vector to other . I tried several ways of assigning the values but could not get it right. Also ,I want to assign a variable 'i' to a constant value in the loop . Below is the code . I have highlighted the lines where I am getting error. I would really appreciate if anyone could help in this . Thank you. 

 

#include "systemc.h"
SC_MODULE(S_R){
sc_in <bool> clk;
sc_in < sc_bv<8> > din;
sc_in <bool> rst;
sc_out< sc_bv<8> > dout;
sc_in<bool> load;
 
sc_bv<8> dinp;
sc_int<1> i ;
 
 
void shift()
{
if(rst)
{
dout=0;
}
else if(load)
{
dinp=din;
i.write('0');
dout[0].write(dinp[7]);
cout<<sc_time_stamp()<<"\tDESIGN1 --> input data:"<<dinp<<"\toutput data:"<<dout<<"\n";
}
else
{
dinp=dinp<<1;
dout[i].write(dinp[7]);
i=i+1;
cout<<sc_time_stamp()<<"\tDESIGN --> input data:"<<dinp<<"\toutput data:"<<dout<<"\n";
 
}
 
}
 
 
SC_CTOR(S_R)
{
SC_METHOD(shift);
sensitive<<clk.pos();
 
}
 
};
 

primitive and hierarchical channel

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Hi Guys,
I am a bit confused on the primitive and hierarchical channel
In primitive channels we have request-update/update but not in hierarchical channel.
Is it mandatory to have request-update/update for primitive channels ? Why ?
Why it is not needed for hierarchical channel

Thanks
RahulJn

How to compile Systemc on MinGW / MSYS?

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Hi

   I tried to compile systemC on MSYS Windows.  I got error. Can anybody help me?  I also pasted the config.log

11150148_10153256198113470_8351948678298

 

This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
 
It was created by SystemC configure 2.3.1, which was
generated by GNU Autoconf 2.69.  Invocation command line was
 
  $ ../configure --target=mingw32
 
## --------- ##
## Platform. ##
## --------- ##
 
hostname = LiuKe-PC
uname -m = i686
uname -r = 1.0.18(0.48/3/2)
uname -s = MINGW32_NT-6.1
uname -v = 2012-11-21 22:34
 
/usr/bin/uname -p = unknown
/bin/uname -X     = unknown
 
/bin/arch              = unknown
/usr/bin/arch -k       = unknown
/usr/convex/getsysinfo = unknown
/usr/bin/hostinfo      = unknown
/bin/machine           = unknown
/usr/bin/oslevel       = unknown
/bin/universe          = unknown
 
PATH: .
PATH: /usr/local/bin
PATH: /mingw/bin
PATH: /bin
PATH: /c/ProgramData/Oracle/Java/javapath
PATH: /c/Program Files (x86)/NVIDIA Corporation/PhysX/Common
PATH: /c/Program Files/NVIDIA GPU Computing Toolkit/CUDA/v6.5/bin
PATH: /c/Program Files/NVIDIA GPU Computing Toolkit/CUDA/v6.5/libnvvp
PATH: /c/Windows/system32
PATH: /c/Windows
PATH: /c/Windows/System32/Wbem
PATH: /c/Windows/System32/WindowsPowerShell/v1.0/
PATH: /c/Program Files (x86)/Windows Kits/8.1/Windows Performance Toolkit/
PATH: /c/Program Files/Microsoft SQL Server/110/Tools/Binn/
PATH: /c/Program Files/MATLAB/MATLAB Production Server/R2015a/runtime/win64
PATH: /c/Program Files/MATLAB/MATLAB Production Server/R2015a/bin
PATH: /c/MinGW_Toolchains/mingw64/bin
PATH: /usr/bin
PATH: /c/Imperas/bin/Windows64
PATH: /c/Imperas_Eclipse/Windows32/Eclipse/jre/bin
 
 
## ----------- ##
## Core tests. ##
## ----------- ##
 
configure:2373: checking build system type
configure:2387: result: i686-pc-mingw32
configure:2407: checking host system type
configure:2420: result: i686-pc-mingw32
configure:2440: checking target system type
configure:2453: result: i386-pc-mingw32
configure:2496: checking for a BSD-compatible install
configure:2564: result: /bin/install -c
configure:2575: checking whether build environment is sane
configure:2625: result: yes
configure:2766: checking for a thread-safe mkdir -p
configure:2805: result: /bin/mkdir -p
configure:2818: checking for gawk
configure:2834: found /bin/gawk
configure:2845: result: gawk
configure:2856: checking whether make sets $(MAKE)
configure:2878: result: yes
configure:2944: checking how to create a pax tar archive
configure:2957: tar --version
tar (GNU tar) 1.23
Copyright © 2010 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>.
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
 
Written by John Gilmore and Jay Fenlason.
configure:2960: $? = 0
configure:3000: tardir=conftest.dir && eval tar --format=posix -chf - "$tardir" >conftest.tar
configure:3003: $? = 0
configure:3007: tar -xf - <conftest.tar
configure:3010: $? = 0
configure:3023: result: gnutar
configure:3042: checking whether make supports nested variables
configure:3059: result: yes
configure:3186: checking for C++ compiler version
configure:3195: g++ --version >&5
g++.exe (GCC) 4.8.1
Copyright © 2013 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO

inout port binding issue

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Hello all,

 

I  am trying to bind 'inout' port named sda in two different modules in a  top module. But it is showing the below error  when I am executing it.

Error: (E109) complete binding failed: port not bound: port '_top_.sr0.port_5' (sc_in)

 

Please find the top module and the two submodules in the attachment.

 

Thank you.

 

 

 

 

Attached Files

SystemC Assertion Library

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Hi all,

 

Please, I would like to know if someone here is aware of any update/progress related to the "Implementation of a SystemC Assertion Library" developed by Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten and Jacob Smit.

 

Is that library available for download ?

 

Thanks in advance,

Fabio

systemC

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Hi,

I am a beginner in systemC and i want to know if i can connect it to quartus.

Is that possible??

Data sampling in SC?

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Hi,

 

I have 3 components in system. Two in SC [Tx and Rx] and One in SV.

Two SC modules are connected in sc_main which is exported. SV is connected via UVM Connect.

 

Tx is driving clock and few signals to Rx. Rx is sampling signals on posedge of clock driven by Tx.

SV component is also sampling same set of signals on posedge of clock which is driven by Tx.

 

Tx is driving clock via sc_out<bool> and Rx is receiving clock via sc_in<bool>.

 

Problem is when Tx drives some signals on posedge of clock, Rx receives change in signals at the same time....where as SV component sees same change on next posedge.

 

Q - Is this how SC/SV event scheduler is expected?

Q - If not then what is the remedy?

 

Dhaval


Port Encapsulation

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Hello, I am working on a model where I am attempting to encapsulate ports. The following code groups sc_in/sc_out ports together based on what bus they belong to. Then I can use arrays to declare the desired number of each type of bus. 

 

template <typename T_ADDR, typename T_DATA>

class ReadBus {
public:
sc_in<T_ADDR>   address;
sc_out<T_DATA> data;
};
 
template <typename T_ADDR, typename T_DATA>
class WriteBus {
public:
sc_in<T_ADDR>  address;
sc_in<bool>         wen;
sc_in<T_DATA>  data;
};
 
class someblock<T_ADDR, T_DATA, n_rp, n_wp> : public sc_module {
...
public:
sc_in_clk clock;
ReadBus<T_ADDR, T_DATA> read_ports[n_rp];
WriteBus<T_ADDR, T_DATA> write_ports[n_wp];
...
}
 

The model compiles and simulates fine but I am wondering if this is synthesizable?

 

It isn't clear to me from looking at the public draft of the synthesizable subset if this is supported. I don't have access to any vendor tools at the moment or I'd try it directly...

 

 

 

SystemC load modules at runtime

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Hi,

 

I am currently trying to load modules from external dlls into a systemc application.

Basic info:

compiler gcc (from cygwin) x64 bit

os: windows 7

 

Also I am using Systemc-AMS but as this appears to be a "problem" with the systemc core I posted it in this forum (feel free to move if inappropriate).

 

The modules are build as shared libs and can can be loaded without problems (using the LoadLibrary function). While I can connect the ports with signals the runtime complains about "no driver" during simulation.

As the same code compiled directly into the application works I assume it is not a problem with the SystemC code itself but with the core not "recognizing" the modules.

 

I read on stackoverflow (http://stackoverflow.com/questions/13794659/loading-systemc-modules-dynamically-at-run-time) that someone had a similar problem once but no solution was posted.

 

Has anyone ever done something similar and is able to help?

 

 

schuschu

Any method of stopping simulation without sc_start(time) and sc_stop

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Hi All,

 

I have built a simulator which uses system C library. Its a network simulator and i am planning to run some traces. Well earlier when i was running my own generated traffic i was specifying the simulation time in cycles and used to achieve results. Now when i am running traces, i am not sure how much time will be enough. i want to ask that is there any way to stop the simulation at any part of the code apart from main(). If yes then how??

I will like to stop the simulation as soon as i am finished processing the last line of my trace file OR i don't receive any more packets in the receiving module designed in my network simulator in a certain time.

Well to be honest i am a novice in system C. I took an introductory class and started building this as it ensured parallel processing.

 

Thank You

Regards

Biplab

Problem with multiple process|Threads and runtime error E115 of multiple writers

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Hello,

 

I'm trying to model a packet switcher, for such I broke the packet assignment of different ports in different methods, because I need to evaluate each port in parallel, however the system complains of multiple access at the same signal. To try to avoid this, before execution, I had a sc_mutex placed, but it didn't seem to have worked, my code follows the following ruleset (I'll copy only two methods to avoid long threads):

enum sqstate_t {SQINIT,SQIDLE,LRS0,LRS1, LRS2,LRS2N,LRS2S,LRS2W,LRS2E};

sc_signal < sqstate_t > sqControlQ0;
sc_signal < sqstate_t > sqControlQ1;

 sc_mutex _qmux;
void SwitchFabric::sendDataQueues0(){
    Packet _temp;
    if(rstn.read() == false){
    if(_qmux.trylock() > 0){
            _bufferIn_read[0].write(false);
            _bufferOut_write[0].write(false);
            _qmux.unlock();
        }
    
        sqControlQ0 = SQINIT;

    }
    else{


        //TODO: Working to transform it into a FSM
        /**
         * Cycle across multiple queues
         */
        switch(sqControlQ0){
        case SQINIT:

            _bufferIn_read[0].write(false);
            _bufferOut_write[0].write(false);
            sqControlQ = SQIDLE;
            break;
        case SQIDLE:
            //for(int i = 0; i < _NPORTS; i++){
                if(_bufferIn_busyOut[0].read() != false){
                    _temp = _inpktOut[0].read();
                    _bufferIn_read[0].write(true);
                    sqControlQ0 = LRS0;
                }
                else{
                    _bufferIn_read[0].write(false);
                    sqControlQ0 = SQIDLE;
                }
            //}
            break;
        case LRS0:
            _bufferIn_read[0].write(false);
            sqControlQ0 = LRS1;
            break;
        case LRS1:
            if(addressing_logic){
                    if(_bufferOut_busyIn[1].read() == false){
                        if(_qmux.trylock() > 0){
                            _outpktIn[1].write(_temp);
                            _bufferOut_write[1].write(true);
                            //_qmux.unlock();
                            sqControlQ0 = LRS2S;
                        }
                        else{
                            sqControlQ0 = LRS1;
                        }

                    }
                    else{
                        sqControlQ0 = LRS1;
                    }
                }
                else
                {
                    if(_bufferOut_busyIn[3].read() == false){
                        if(_qmux.trylock() > 0){
                            _outpktIn[3].write(_temp);
                            _bufferOut_write[3].write(true);
                            //_qmux.unlock();
                            sqControlQ0 = LRS2E;
                        }
                        else{
                            sqControlQ0 = LRS1;
                        }

                    }
                    else{
                        sqControlQ0 = LRS1;
                    }
                }
            }
            else{
                if(addressing_logic){
                    if(_bufferOut_busyIn[2].read() == false){
                        if(_qmux.trylock() > 0){
                            _outpktIn[2].write(_temp);
                            _bufferOut_write[2].write(true);
                            //_qmux.unlock();
                            sqControlQ0 = LRS2W;
                        }
                        else{
                            sqControlQ0 = LRS1;
                        }

                    }
                    else{
                        sqControlQ0 = LRS1;
                    }
                }
                else
                {
                    if(_bufferOut_busyIn[0].read() == false){
                        if(_qmux.trylock() > 0){
                            _outpktIn[0].write(_temp);
                            _bufferOut_write[0].write(true);
                            //_qmux.unlock();
                            sqControlQ0 = LRS2N;
                        }
                        else{
                            sqControlQ0 = LRS1;
                        }

                    }
                    else{
                        sqControlQ0 = LRS1;
                    }
                }
            }
            break;

        case LRS2N:
            _bufferOut_write[0].write(false);
            _qmux.unlock();
            sqControlQ0 = SQIDLE; //TODO: or maybe some other state
            break;
        case LRS2S:
            _bufferOut_write[1].write(false);
            _qmux.unlock();
            sqControlQ0 = SQIDLE; //TODO: or maybe some other state
            break;
        case LRS2W:
            _bufferOut_write[2].write(true);
            _qmux.unlock();
            sqControlQ0 = SQIDLE; //TODO: or maybe some other state
            break;
        case LRS2E:
            _bufferOut_write[3].write(true);
            _qmux.unlock();
            sqControlQ0 = SQIDLE; //TODO: or maybe some other state
            break;
        default:
            break;
        }



    }

}
void SwitchFabric::sendDataQueues1(){
    Packet _temp;

    if(rstn.read() == false){


        if(_qmux.trylock() > 0){
            _bufferIn_read[1].write(false);
            _bufferOut_write[1].write(false);
            _qmux.unlock();
        }

        sqControlQ1 = SQINIT;

    }
    else{


        //TODO: Working to transform it into a FSM
        /**
         * Cycle across multiple queues
         */
        switch(sqControlQ1){
        case SQINIT:
            //for(int i = 0; i < _NPORTS; i++){
            _bufferIn_read[1].write(false);
            _bufferOut_write[1].write(false);
            //}

            sqControlQ = SQIDLE;
            break;
        case SQIDLE:
            //for(int i = 0; i < _NPORTS; i++){
                if(_bufferIn_busyOut[1].read() != false){
                    _temp = _inpktOut[1].read();
                    _bufferIn_read[1].write(true);
                    sqControlQ1 = LRS0;
                }
                else{
                    _bufferIn_read[1].write(false);
                    sqControlQ1 = SQIDLE;
                }
            //}
            break;
        case LRS0:
            _bufferIn_read[1].write(false);
            sqControlQ1 = LRS1;
            break;
        case LRS1:
            if(Adressing_logic){
                    if(_bufferOut_busyIn[1].read() == false){
                        if(_qmux.trylock() > 0){
                            _outpktIn[1].write(_temp);
                            _bufferOut_write[1].write(true);
                            //_qmux.unlock();
                            sqControlQ1 = LRS2S;
                        }
                        else{
                            sqControlQ1 = LRS1;
                        }

                    }
                    else{
                        sqControlQ1 = LRS1;
                    }
                }
                else
                {
                    if(_bufferOut_busyIn[3].read() == false){
                        if(_qmux.trylock() > 0){
                            _outpktIn[3].write(_temp);
                            _bufferOut_write[3].write(true);
                            //_qmux.unlock();
                            sqControlQ1 = LRS2E;
                        }
                        else{
                            sqControlQ1 = LRS1;
                        }

                    }
                    else{
                        sqControlQ1 = LRS1;
                    }
                }
            }
            else{
                if(Adressing_logic2)
                ){
                    //this->_bufferOut[1].dataIn = _temp;
                    if(_bufferOut_busyIn[2].read() == false){
                        if(_qmux.trylock() > 0){
                            _outpktIn[2].write(_temp);
                            _bufferOut_write[2].write(true);
                            //_qmux.unlock();
                            sqControlQ1 = LRS2W;
                        }
                        else{
                            sqControlQ1 = LRS1;
                        }

                    }
                    else{
                        sqControlQ1 = LRS1;
                    }
                }
                else
                {
                    if(_bufferOut_busyIn[0].read() == false){
                        if(_qmux.trylock() > 0){
                            _outpktIn[0].write(_temp);
                            _bufferOut_write[0].write(true);
                            //_qmux.unlock();
                            sqControlQ1 = LRS2N;
                        }
                        else{
                            sqControlQ1 = LRS1;
                        }

                    }
                    else{
                        sqControlQ1 = LRS1;
                    }
                }
            }
            break;

        case LRS2N:
            _bufferOut_write[0].write(false);
            _qmux.unlock();
            sqControlQ1 = SQIDLE; //TODO: or maybe some other state
            break;
        case LRS2S:
            _bufferOut_write[1].write(false);
            _qmux.unlock();
            sqControlQ1 = SQIDLE; //TODO: or maybe some other state
            break;
        case LRS2W:
            _bufferOut_write[2].write(true);
            _qmux.unlock();
            sqControlQ1 = SQIDLE; //TODO: or maybe some other state
            break;
        case LRS2E:
            _bufferOut_write[3].write(true);
            _qmux.unlock();
            sqControlQ1 = SQIDLE; //TODO: or maybe some other state
            break;
        default:
            break;
        }



    }

}

Please, if anyone could advise me on how to proceed to have this as parallel process in any way, even if I have to t everything in the same process, but working as Threads I would appreciate it.

 

P.S.: I saw in the internet people saying to use export SC_SIGNAL_WRITE_CHECK=DISABLE, and the problem disappear, it may disappear, but I'm not sure if this is the right fix in this case.

Object Oriented programming using SystemC

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Hi

 

From what I have seen, SystemC throws error while attempting to use Inheritance/polymorphism.

 

For example

 

I have a Task 

 

SC_MODULE(Task)

{

sc_in<bool> in;

sc_in<bool> out;

 

void cliamResource()

{....}

 

void claimMemory()

{......}

 

 

SC_CTOR(Task)

{}

};

 

Like Wise i have a Resource Module :

 

And then I have number of C++ classes( class A, class B which defines each function I am using).

 

But I am not able to inherit these normal c++ classes like 

 

SC_MODULE(Task) : public A            \\ where A is a Class A

{};

 

 

Can anyone help me how t sort this out (or) Is it possible to inherit C++ classes ??

 

I have a error like : class or struct definition is missing

 

 

Thanks

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