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Problem in TLM READ command

January 1, 2015, 11:35 pm
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Hi all,

 

I'm getting problem in TLM read command .Please check the code once is am doing right ?Then why it's not reading correct value's?

 

  In read function.....i'm going through b_transport....

 

    tlm::tlm_generic_payload* trans=new tlm::tlm_generic_payload;
    sc_time delay=sc_time(0,SC_NS);
    trans->set_command(tlm::TLM_READ_COMMAND);
    trans->set_address(addr);
    if((dmi_valid)&&(addr >=dmi_data.get_start_address()) && (addr<=dmi_data.get_end_address())){
        SC_REPORT_INFO_VERB("Traffic_injector","dmi access",2);
    }else {
        SC_REPORT_INFO_VERB("traffic injector","READ:normal access....",2);
        trans->set_data_ptr(reinterpret_cast<unsigned char*>(data));
        trans->set_data_length(length);
        trans->set_byte_enable_ptr(0);
        trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
        initiator_socket->b_transport(*trans,delay);
        if(trans->is_response_error()){
            SC_REPORT_ERROR("TLM-2","response error from b_transport");
        }
        unsigned char* data_ptr=trans->get_data_ptr();

 

 

  In b_transport ....

      tlm::tlm_command cmd=trans.get_command();
      uint8_t addr=trans.get_address();
      unsigned char* data_ptr=trans.get_data_ptr();
      unsigned int len=trans.get_data_length();
        
      if(cmd==tlm::TLM_READ_COMMAND){
        
            bool flag=(bool)((device_rx_data[addr]>>len)& 0x1);

             data_ptr=reinterpret_cast<unsigned char*>(&flag);

      }
 

 

In b_transport it setting correct values to data_ptr (as am checked in debugger).But in read

    unsigned char* data_ptr=trans->get_data_ptr();

am getting always zero...Is am doing right casting ?If not tell correct path?

 

Thanks,

Pruthvi

 

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sensitivity list in systemc

January 5, 2015, 6:13 am
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Hi

 

I am thinking of moving from verilog to systemc for hardware design.

I have a question about sensitivity list: When I am implementing a logic cloud (not clocked) in verilog, I use the "always @* begin" construct to ensure that all the inputs are in the sensitivity list.

 

Is there a similar construct in systemc, where I don't have to explicitly list all the inputs that can cause the output to change?

 

thanks,

Venkat.

 

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Ugg Boots Sale Usa

January 6, 2015, 12:55 am
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Channel vs port value update

August 14, 2014, 6:44 am
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Hello everybody,

While working on a systemC project, I discovered that probably I have some confused ideas about signals and ports. Let's say I have something like this:

 

//cell.hpp

SC_MODULE(Cell)
{ 
   sc_in<sc_uint<16> > datain; 
   sc_in<sc_uint<1> > addr_en;
   sc_in<sc_uint<1> >  enable;
   sc_out<sc_uint<16> > dataout;
  
   SC_CTOR(Cell)
   {
     SC_THREAD(memory_cell);
        sensitive << enable << datain << addr_en;
   }
   private:
   void memory_cell();
};

 

//cell.cpp

void Cell::memory_cell()
{  
   unsigned short data_cell=11;
        
   while(true)
   {     
      //wait for some input
      wait();     
           
      if (enable->read()==1 && addr_en->read()==1)
      {        
         data_cell=datain->read();        
      }
      
      else
      {
         if(enable->read()==0 && addr_en->read()==1)
         {
            dataout->write(data_cell);
         }
     }
   }
}

 

 

//test.cpp

SC_MODULE(TestBench)
{
   sc_signal<sc_uint<1> > address_en_s;
   sc_signal<sc_uint<16> > datain_s;  
   sc_signal<sc_uint<1> >  enable_s;
   sc_signal<sc_uint<16> > dataout_s;   
    
   Cell cella;
   
   SC_CTOR(TestBench) : cella("cella")
   {
        // Binding
        cella.addr_en(address_en_s);
        cella.datain(datain_s);
        cella.enable(enable_s);
        cella.dataout(dataout_s);               
        SC_THREAD(stimulus_thread);                        
   }


  private:
    void stimulus_thread() {  

//write a value:    
        datain_s.write(81);    
        address_en_s.write(1);    
        enable_s.write(1);         
        wait(SC_ZERO_TIME);
       

//read what we have written:
        enable_s.write(0);
        address_en_s.write(1);
        wait(SC_ZERO_TIME);
                 
        cout << "Output value: " << dataout_s.read() << endl;
        

//let's cycle the memory again:       
        address_en_s.write(0);         
        wait(SC_ZERO_TIME);
        cout << "Output value: " << dataout_s.read() << endl;
       
    }   
};

 

 

I've tried running this modules and I've noticed something weird (at least, weird for me): when the stimulus writes a value (81), after the wait(SC_ZERO_TIME) the memory thread finds its datain, enable and address_enable values already updated. This is what I expected to happen. The same happens when the stimulus changes the enable_es value, in order to run another cycle in the memory thread and copy the datacell value into the memory cell dataout port. What I don't understand is why after the memory module writes into its dataout port and goes again to the wait() statement at the beginning of the while loop, the stimulus module still has the old value on its dataout_s channel (0), and not the new value(81), which has just been copied by the memory module. Then, if I run another cycle of the memory loop (for example changing some values on the stimulus channels), the dataout channel finnally updates.

In other words, it looks like that if I write into the stimulus channels and then switch to the memory thread, the memory finds the values updated. But if the memory thread writes into its ports, and then i switch to the stimulus thread, the thread still sees the old values on its channels (binded to the memory ports).

 

I don't know if I am clear, and I am sure that maybe this is a naive question, but i am a newbie with systemC and I need to understand this thing.

 

 

 

 

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SystemC - Inconsistent result

January 7, 2015, 11:15 am
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Hello all,

 

I'm simulating MOESI protocol for L1 caches in SystemC. I'm getting different results for the same source code when running in SystemC 2.3.0 and SystemC 2.3.1 versions in different machines. Could anyone kindly pass some light on this topic?

 

Machine1:

Linux 3.13, Ubuntu 14.04, SystemC 2.3.1, Intel Pentium Dual Core processor.

Output - Machine 1:

CPU    Reads    RHit    RMiss    Writes    WHit    WMiss    Hitrate
0    6    0    6    4    0    4    0.000000
1    34    0    34    22    0    22    0.000000
2    35    0    35    43    0    43    0.000000
3    39    2    37    46    2    44    4.705882
4    36    0    36    55    0    55    0.000000
5    52    0    52    47    0    47    0.000000
6    48    3    45    51    2    49    5.050505
7    42    1    41    55    5    50    6.185567
Total:    292    6    286    323    9    314    15
Avg:    36    0    35    40    1    39    1
2. Main memory access rates
    Bus had 286 reads and 1 upgrades and 314 readX.
    A total of  601  accesses.
3. Average time for bus acquisition
    There were 50 waits for the bus.
    Average waiting time per access: 0.083195 cycles.
4. There were 1 Cache to Cache transfers
5. Total execution time is 10204 ns, Avg per-mem-access time is 16.978369 ns
6. Probe Read: 5,     Probe ReadX: 7 

Machine 2:

Linux 3.13, Ubuntu 14.04, SystemC 2.3.0, Intel i7 Quad Core processor.

Output - Machine 2:

CPU    Reads    RHit    RMiss    Writes    WHit    WMiss    Hitrate
0    6    0    6    4    0    4    0.000000
1    34    0    34    22    0    22    0.000000
2    35    0    35    43    0    43    0.000000
3    39    2    37    46    2    44    4.705882
4    36    0    36    55    0    55    0.000000
5    52    0    52    47    0    47    0.000000
6    48    3    45    51    2    49    5.050505
7    42    1    41    55    5    50    6.185567
2. Main memory access rates
    Bus had 286 reads and 0 upgrades and 314 readX.
    A total of 600 accesses.
3. Average time for bus acquisition
    There were  51  waits for the bus.
    Average waiting time per access: 0.085000 cycles.
4. There were 0 Cache to Cache transfers
5. Total execu tion time is 10204 ns, Avg per-mem-access time is 17.006667 ns
6. Probe Read:  1 ,     Probe ReadX: 0 

Does the version 2.3.0 and 2.3.1 are the reason for the inconsistent result?

Source code and steps to run the simulation can be found here.

 

Thanks,

Tamilselvan Shanmugam.

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Parallel Schedular

January 8, 2015, 1:26 am
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Hi - I wish to know if the latest systemC kernel version scheduler supports parallelization. I have went through the documentations on site, it seems the only form of parallelization supported is through TLM? Can you please confirm

 

 

Regards,

Mustafa 

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function with wait

January 12, 2015, 3:55 am
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Hello all,

 

I have doubt regarding use of c++ function inside systemc threads.

It is said that a normal c++ function which is declared in a class inherting systemc module and called  inside the thread of that class shall be executed based  c++ kernel simulation not on the basis of systemc scheduler therefor it won't  wait for an event or time if introduced in it. Is that true ? But in my code nothing as such is happening the function is waiting for time introduced in it.

 

Regards.   

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Want to lear "System C " in order to study Embedded system course

January 14, 2015, 2:11 pm
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Can any please tell what is the best way to learn "system C" in detail so that can work on my university projects. Any sort of Book suggestions will be very helpful Thank you.

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I wonder will this work

January 19, 2015, 5:54 pm
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SYSTEMC install 32bit on 64bit OS

January 22, 2015, 7:49 am
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Hi,

 

I want install systemc 32bit on my 64bit host.

 

I follow the website comment.

 cd $SYSTEMC_HOME/objdir
  ../configure --target=i686-linux-gnu

  # QuickThreads:
  make CPPFLAGS="-m32" AS="as --32"

  # Pthreads:
  make CPPFLAGS="-m32" QT_ARCH="pthreads" pthreads

  make install

But when I make CPPFLAGS="-m32" AS="as --32",

I have a problem, as following

make[3]: *** [libsystemc.la] Error 1
make[3]: Leaving directory `/root/systemc-2.3.1/src/sysc'
make[2]: *** [all-recursive] Error 1
make[2]: Leaving directory `/root/systemc-2.3.1/src/sysc'
make[1]: *** [all-recursive] Error 1
make[1]: Leaving directory `/root/systemc-2.3.1/src'
make: *** [all-recursive] Error 1

How can I solve the problem?

 

Thank a lot.

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SYSTEMC sensitivity

January 22, 2015, 11:14 pm
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Hello All , 

 I am a beginner in SystemC with Hardware verification background (sv/uvm). I coded a simple synchronous design (sensitive_pos (clk)) and ran the simulation using questasim10.2 . Sadly In waveform the behavior looked as a combination logic rather than a sequential one.

 

Whether its the problem of simulator or systemc ? .Also what will be the best simulator for SystemC.

 

Thanks in advance,

Kavinkumar  (MTS , AtriaLogic). 

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Passing maps within Constructors in SystemC struct

January 27, 2015, 9:04 am
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Hi Experts,

 

How do I pass "Maps" within constructors while using a SystemC struct? 

I want to instantiate this module 4 times and use 4 different maps for each instance.

 

struct Detector: sc_module
{
  

    SC_CTOR(Detector)
   
    {
     

        for (int i = 0 ; i<10 ; i++)
        {
          in_map[i]= map[i][0];  // in_map has been declared as private & map is passed on through the constructor
        }

    }
 

 

Thankyou in advance!

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Naming of ports which inherits sc_signal/in/outs

January 31, 2015, 4:10 am
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Dear All,

 

I have an use case as follows:

 


# include <systemc>


# ifndef M_SIGNAL_H_
# define M_SIGNAL_H_


  template < typename T > 
  class m_signal
     :   public sc_core::sc_signal < T >
  {
     public :
        m_signal (const char* portName_) 
        {
           std::cout << this->name() << std::endl ;
           // I need to assign name!
        }
  };


# endif


  int sc_main(int argc, char* argv[])
  {
  
     m_signal < sc_dt::sc_uint < 21 > > thisSignal("thisSignal") ;
  
     std::cout << thisSignal.name() << std::endl ;
     std::cout << thisSignal.basename() << std::endl ;
     std::cout << thisSignal.kind() << std::endl ;


     return EXIT_SUCCESS ;
  
  }

 

 

I want to give access name() of the parent class. An idea to inherit it will be great and appreciated. This is very important for tracing to work accordingly.

 

Regards,

Sumit

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Availability of adaptor TLM 2.0 to Flash Model interface ?

February 4, 2015, 9:51 pm
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Hi all,

 

Is their any available free source to interface TLM 2.0 to FLASH model (like AMBA to TLM 2.0)?

 

Thanks,

Pruthvi

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Build errors

February 11, 2015, 12:39 am
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Hi to all!I am trying to build a packet switch for a project i am assigned and i have the following errorS
1>  switch_clk.cpp
1>c:\systemc-2.3.1\systemc-2.3.1\src\sysc\datatypes\int\sc_nbutils.h(149): error C4996: 'sprintf': This function or variable may be unsafe. Consider using sprintf_s instead. To disable deprecation, use _CRT_SECURE_NO_WARNINGS. See online help for details.
1>          c:\program files (x86)\microsoft visual studio 12.0\vc\include\stdio.h(356) : see declaration of 'sprintf'
1>  switch.cpp
1>c:\systemc-2.3.1\systemc-2.3.1\src\sysc\datatypes\int\sc_nbutils.h(149): error C4996: 'sprintf': This function or variable may be unsafe. Consider using sprintf_s instead. To disable deprecation, use _CRT_SECURE_NO_WARNINGS. See online help for details.
1>          c:\program files (x86)\microsoft visual studio 12.0\vc\include\stdio.h(356) : see declaration of 'sprintf'
1>  sender.cpp
1>c:\systemc-2.3.1\systemc-2.3.1\src\sysc\datatypes\int\sc_nbutils.h(149): error C4996: 'sprintf': This function or variable may be unsafe. Consider using sprintf_s instead. To disable deprecation, use _CRT_SECURE_NO_WARNINGS. See online help for details.
1>          c:\program files (x86)\microsoft visual studio 12.0\vc\include\stdio.h(356) : see declaration of 'sprintf'
1>  receiver.cpp
1>c:\systemc-2.3.1\systemc-2.3.1\src\sysc\datatypes\int\sc_nbutils.h(149): error C4996: 'sprintf': This function or variable may be unsafe. Consider using sprintf_s instead. To disable deprecation, use _CRT_SECURE_NO_WARNINGS. See online help for details.
1>          c:\program files (x86)\microsoft visual studio 12.0\vc\include\stdio.h(356) : see declaration of 'sprintf'
1>  main.cpp
1>c:\systemc-2.3.1\systemc-2.3.1\src\sysc\datatypes\int\sc_nbutils.h(149): error C4996: 'sprintf': This function or variable may be unsafe. Consider using sprintf_s instead. To disable deprecation, use _CRT_SECURE_NO_WARNINGS. See online help for details.
1>          c:\program files (x86)\microsoft visual studio 12.0\vc\include\stdio.h(356) : see declaration of 'sprintf'
1>  fifo.cpp
1>c:\systemc-2.3.1\systemc-2.3.1\src\sysc\datatypes\int\sc_nbutils.h(149): error C4996: 'sprintf': This function or variable may be unsafe. Consider using sprintf_s instead. To disable deprecation, use _CRT_SECURE_NO_WARNINGS. See online help for details.
1>          c:\program files (x86)\microsoft visual studio 12.0\vc\include\stdio.h(356) : see declaration of 'sprintf'
1>c:\users\zogas\desktop\new folder\packet_switch_final\packet_switch_final\fifo.cpp(7): warning C4244: 'argument' : conversion from 'sc_dt::uint_type' to 'int', possible loss of data
1>  Generating Code...
 
Any help will be appreciated
Regards
Stavros
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SystemC using Visual Studio 2013

February 24, 2015, 11:49 am
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Hello,

 

I'm currently trying to port a SystemC simulation running under Linux to Windows with Visual Studio 2013.

 

I've been searching and following several guides like this one : 

http://www.ict.kth.se/courses/IL2452/Sept2009/TUTORIAL-SystemC-with-Microsoft-Visual-Studio.pdf

 

The only missing option I couldn't set is "detect 64-bit portability issues".

 

Although, when I'm trying to compile a simple SystemC project, the following error occurs :

 

Error 1 error LNK1561: entry point must be defined
 
After looking for it on google, I found this link, saying that the SystemC.lib file might not have been set in VS:
 
The thing is, it is. 
 
Can someone help me?
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Issue with Virtual platform integration

February 26, 2015, 1:52 am
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hello ,

 

I have a virtual platform(versatilepb based) which I am using to validate my Universal flash subsystem(UFS) host controller TLM model.
From OS, when it issue SCSI command, the underlying ufshcd driver make a data packet and put in in system memory. The system memory is allocated using dmam_alloc_coherent. The driver also write the starting address of this memory in UFS host controller register.  You can see this driver  in linux-3.17.2/drivers/scsi/ufs

 
Now when in TLM model I read that register, I get the correct address bus when I try to access this address as
uint8_t data1 = *( uint8_t *) (address);
I am getting segmentation fault.

My question is can I directly access system memory address in TLM model as I am doing above or I need to do something special.

 

Thanks
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A question of semaphore channel in SystemC

March 2, 2015, 8:47 am
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Hi everyone,
 
Recently, I am studying systemc and have a problem on semaphore channel.
 
Actually, I found an example of semaphore channel on asic world (http://www.asic-world.com/systemc/channels3.html). This example provides 3 processes (SC_CTHREAD): bus_semaphore(), do_read() and do_write(). like below,
 
-------------------------------------------------------------------------------------------------------
#include <systemc.h>

SC_MODULE (sc_semaphore_example) {
sc_in<bool> clock;

sc_semaphore bus;
int cnt;

void bus_semaphore() {
while (true) {
wait();
cout << "@" << sc_time_stamp() <<" Check if semaphore is 0 " << endl;
if (bus.get_value() == 0) {
cout << "@" << sc_time_stamp() <<" Posting 2 to semaphore " << endl;
bus.post();
bus.post();
if (cnt >= 3) {
sc_stop(); // sc_stop triggers end of simulation
}
cnt ++;
}
}
}

void do_read() {
while (true) {
wait();
cout << "@" << sc_time_stamp() <<" Checking semaphore for intance 0"<<endl;
// Check if semaphore is available
if (bus.trywait() != -1) {
cout << "@" << sc_time_stamp() <<" Got semaphore for intance 0"<<endl;
wait(2);
}
}
}

void do_write() {
while (true) {
wait();
cout << "@" << sc_time_stamp() <<" Checking semaphore for intance 1"<<endl;
// Wait till semaphore is available
bus.wait();
cout << "@" << sc_time_stamp() <<" Got semaphore for intance 1"<<endl;
wait(3);
}
}

SC_CTOR(sc_semaphore_example) : bus(0){
cnt = 0;
SC_CTHREAD(do_read,clock.pos());
SC_CTHREAD(do_write,clock.pos());
SC_CTHREAD(bus_semaphore,clock.pos());
}
};

int sc_main (int argc, char* argv[]) {
sc_clock clock ("my_clock",1,0.5);

sc_semaphore_example object("semaphore");
object.clock (clock.signal());

sc_start(0); // First time called will init schedular
sc_start(); // Run the simulation till sc_stop is encountered
return 0;// Terminate simulation
}
===================== simulation result given ====================
@1 ns Check if semaphore is 0
@1 ns Posting 2 to semaphore
@1 ns Checking semaphore for intance 1
@1 ns Got semaphore for intance 1
@1 ns Checking semaphore for intance 0
@1 ns Got semaphore for intance 0
@2 ns Check if semaphore is 0
@2 ns Posting 2 to semaphore
@3 ns Check if semaphore is 0
@4 ns Check if semaphore is 0
@4 ns Checking semaphore for intance 0
@4 ns Got semaphore for intance 0
@5 ns Check if semaphore is 0
@5 ns Checking semaphore for intance 1
@5 ns Got semaphore for intance 1
@6 ns Check if semaphore is 0
@6 ns Posting 2 to semaphore
@7 ns Check if semaphore is 0
@7 ns Checking semaphore for intance 0
@7 ns Got semaphore for intance 0
@8 ns Check if semaphore is 0
@9 ns Check if semaphore is 0
@9 ns Checking semaphore for intance 1
@9 ns Got semaphore for intance 1
@10 ns Check if semaphore is 0
@10 ns Posting 2 to semaphore
@10 ns Checking semaphore for intance 0
@10 ns Got semaphore for intance 0
---------------------------------------------------------------------------------------------------------
 
There might be a problem about the former two threads.
 
At the first 1ns for this example, the first process bus_semaphore() works and can print out all of the two lines like "@1 ns ....". At the same time in this thread then, the semaphore value (bus) changes into 2 (bus.post()). Then this thread will wait for the next clock posedge. So far everything is good.
 
For the second process, do_read(), also at the 1ns, the first "@" line can be printed out normally, but then what about the expression trywait() in the next if-statement? The first and second process should start to work at the same time (all have wait()at the beginning), that is to say we cannot determine whether the trywait() (in the second process) executes before or after the bus.post() statement (in the first process), so we don't know if the second "@" line of the second process will be printed out.
 
But the simulation result shows that the trywait() will execute after the bus.post() executes such that the second "@..." statement in the second process will be printed out. My question is how can I be sure that the trywait() will execute after the bus.post()'s execution? Shouldn't they execute simultaneously?
 
Thanks a lot!
Wayne
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Syntax questions on systemC

March 5, 2015, 9:00 am
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Hi,

 

I have some questions on systemC syntax. 

 

1. sc_event_queue. I found a lot of examples for sc_event_queue on some systemC coursewares (even threads on this forum), like below,

 
SC_MODULE(somemod){
     sc_event_queue eq;
     ...
     void process1(){
          while(true){
          ...
          wait(eq);                       // here got a message: cannot convert from 'sc_core::sc_event_queue' to 'const sc_core::sc_event' ,
          ...
          }
     }
     void process2(){
          while(true){
         ...
         eq.notify(5,SC_NS);
         eq.notify(8,SC_NS);
         ...
          }
     }
     SC_CTOR(somemod){
     ...
     }
};
    If I change "wait(eq)" into "wait(eq.default_event())" or just use "wait()" meanwhile add eq into the sensitive list, it will work. Is it correct?
 
2. sc_semaphore channel. I see an example from the book systemc from the ground up like this,
 
SC_MODULE(gas_station) {
     sc_semaphore pump(12);      // here seems define a function which will return a sc_semaphore instance
     void customer1_thread {
          for(;; ) {
          // wait till tank empty 
          …
          // find an available gas pump
          pump.wait();
          // fill tank & pay
     }
};
    But this seems that it cannot work at all. Then if I use a new form like below it will work,
 
SC_MODULE(gas_station) {
     sc_semaphore pump;      
     void customer1_thread {
          for(;; ) {
          // wait till tank empty 
          …
          // find an available gas pump
          pump.wait();
          // fill tank & pay
     }
     SC_CTOR: pump(12){
     ...
     }
};
    So if I want to use the form of sc_semaphore pump(12) to the module, what should I do on the constructor?
 
Another question for the semaphore channel: does the sc_semaphore value have a upper limit or what is the size of this channel?
 
Thanks a lot!
 
Wayne
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Makefile error

March 8, 2015, 11:14 pm
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hi i am getting the following error while running makefile

 

lord@lord-Inspiron-N5050:~/systemc-2.3.1/examples/sysc$ gmake -f Makefile.all TARGET_ARCH=linux64 run
gmake[1]: Entering directory `/home/lord/systemc-2.3.1/examples/sysc/fir'
gmake[2]: Entering directory `/home/lord/systemc-2.3.1/examples/sysc/fir'
../Makefile.rules:99: *** SystemC library [/usr/local/systemc230//lib-linux64] not found. Please update Makefile.config.  Stop.
gmake[2]: Leaving directory `/home/lord/systemc-2.3.1/examples/sysc/fir'
gmake[2]: Entering directory `/home/lord/systemc-2.3.1/examples/sysc/fir'
../Makefile.rules:99: *** SystemC library [/usr/local/systemc230//lib-linux64] not found. Please update Makefile.config.  Stop.
gmake[2]: Leaving directory `/home/lord/systemc-2.3.1/examples/sysc/fir'
gmake[1]: *** [run] Error 2
gmake[1]: Leaving directory `/home/lord/systemc-2.3.1/examples/sysc/fir'
gmake: *** [run] Error 2
 

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