Hi ,
Recently I have studied that SystemC can be used To model High level functional models to detailed clock cycle accurate RTL models.
If any company done like this then the they can save the time and energy too. Because at different levels we are using the same language.
But as of my knowledge many companies uses SystemC at system Modeling only.
Why they are not using the same language at RTL instead it has many advantages. ?
Please clear this doubt
Thanks,
Mani
Hello All,
I need some strong suggestion regarding modeling of TIMER.
I am new in systemc.
Want to know what are the things a best model should consist of and how its modeling should be done ?
Since timer has a clock time period,
should i model it in by incrementing/decrementing the counter and applying a delay for timer period
or i should model it without any delay by using sensitivity to the new write in register and decremnting/ incrementing the counter value by evaluating the current time period and previous sensitivity time period by clock time period.
With Warm Regards.
Hi all,
I'm getting problem in TLM read command .Please check the code once is am doing right ?Then why it's not reading correct value's?
In read function.....i'm going through b_transport....
tlm::tlm_generic_payload* trans=new tlm::tlm_generic_payload;
sc_time delay=sc_time(0,SC_NS);
trans->set_command(tlm::TLM_READ_COMMAND);
trans->set_address(addr);
if((dmi_valid)&&(addr >=dmi_data.get_start_address()) && (addr<=dmi_data.get_end_address())){
SC_REPORT_INFO_VERB("Traffic_injector","dmi access",2);
}else {
SC_REPORT_INFO_VERB("traffic injector","READ:normal access....",2);
trans->set_data_ptr(reinterpret_cast<unsigned char*>(data));
trans->set_data_length(length);
trans->set_byte_enable_ptr(0);
trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
initiator_socket->b_transport(*trans,delay);
if(trans->is_response_error()){
SC_REPORT_ERROR("TLM-2","response error from b_transport");
}
unsigned char* data_ptr=trans->get_data_ptr();
In b_transport ....
tlm::tlm_command cmd=trans.get_command();
uint8_t addr=trans.get_address();
unsigned char* data_ptr=trans.get_data_ptr();
unsigned int len=trans.get_data_length();
if(cmd==tlm::TLM_READ_COMMAND){
bool flag=(bool)((device_rx_data[addr]>>len)& 0x1);
data_ptr=reinterpret_cast<unsigned char*>(&flag);
}
In b_transport it setting correct values to data_ptr (as am checked in debugger).But in read
unsigned char* data_ptr=trans->get_data_ptr();
am getting always zero...Is am doing right casting ?If not tell correct path?
Thanks,
Pruthvi
Hi
I am thinking of moving from verilog to systemc for hardware design.
I have a question about sensitivity list: When I am implementing a logic cloud (not clocked) in verilog, I use the "always @* begin" construct to ensure that all the inputs are in the sensitivity list.
Is there a similar construct in systemc, where I don't have to explicitly list all the inputs that can cause the output to change?
thanks,
Venkat.
Hello all,
I'm simulating MOESI protocol for L1 caches in SystemC. I'm getting different results for the same source code when running in SystemC 2.3.0 and SystemC 2.3.1 versions in different machines. Could anyone kindly pass some light on this topic?
Machine1:
Linux 3.13, Ubuntu 14.04, SystemC 2.3.1, Intel Pentium Dual Core processor.
Output - Machine 1:
CPU Reads RHit RMiss Writes WHit WMiss Hitrate 0 6 0 6 4 0 4 0.000000 1 34 0 34 22 0 22 0.000000 2 35 0 35 43 0 43 0.000000 3 39 2 37 46 2 44 4.705882 4 36 0 36 55 0 55 0.000000 5 52 0 52 47 0 47 0.000000 6 48 3 45 51 2 49 5.050505 7 42 1 41 55 5 50 6.185567 Total: 292 6 286 323 9 314 15 Avg: 36 0 35 40 1 39 1 2. Main memory access rates Bus had 286 reads and 1 upgrades and 314 readX. A total of 601 accesses. 3. Average time for bus acquisition There were 50 waits for the bus. Average waiting time per access: 0.083195 cycles. 4. There were 1 Cache to Cache transfers 5. Total execution time is 10204 ns, Avg per-mem-access time is 16.978369 ns 6. Probe Read: 5, Probe ReadX: 7
Machine 2:
Linux 3.13, Ubuntu 14.04, SystemC 2.3.0, Intel i7 Quad Core processor.
Output - Machine 2:
CPU Reads RHit RMiss Writes WHit WMiss Hitrate 0 6 0 6 4 0 4 0.000000 1 34 0 34 22 0 22 0.000000 2 35 0 35 43 0 43 0.000000 3 39 2 37 46 2 44 4.705882 4 36 0 36 55 0 55 0.000000 5 52 0 52 47 0 47 0.000000 6 48 3 45 51 2 49 5.050505 7 42 1 41 55 5 50 6.185567 2. Main memory access rates Bus had 286 reads and 0 upgrades and 314 readX. A total of 600 accesses. 3. Average time for bus acquisition There were 51 waits for the bus. Average waiting time per access: 0.085000 cycles. 4. There were 0 Cache to Cache transfers 5. Total execu tion time is 10204 ns, Avg per-mem-access time is 17.006667 ns 6. Probe Read: 1 , Probe ReadX: 0
Does the version 2.3.0 and 2.3.1 are the reason for the inconsistent result?
Source code and steps to run the simulation can be found here.
Thanks,
Tamilselvan Shanmugam.
Hi All,
I am a novice in systemC. I am having some doubts in using SC_METHOD().
I am building a network simulator in systemC. And from each node there are about four channels. I want the four channels to work simultaneously. The four channels get data from a common buffer in receiver and then transmit.
So i declared a SC_Module and declared 4 SC_METHOD processes in it corresponding to each channel.
Hi,
I am running cygwin64 on windows 8.1 machine. I am running into below failure while running "make check" while installing SystemC on my machine. Can some one help me?
PASS: rsa/test.sh
SystemC 2.3.1-Accellera --- May 19 2015 17:31:07
Copyright © 1996-2014 by all Contributors,
ALL RIGHTS RESERVED
***ERROR:
0a1,100
> 0 s top.master_d : mem[78:87] = (0, 0, 0, 0)
> 100 ns top.master_d : mem[78:87] = (b, c, d, e)
> 200 ns top.master_d : mem[78:87] = (b, c, d, e)
> 300 ns top.master_d : mem[78:87] = (b, c, d, e)
> 400 ns top.master_d : mem[78:87] = (1b, 1d, d, e)
> 500 ns top.master_d : mem[78:87] = (26, 18, 1a, 2f)
> 600 ns top.master_d : mem[78:87] = (26, 18, 1a, 2f)
> 700 ns top.master_d : mem[78:87] = (26, 18, 1a, 2f)
> 800 ns top.master_d : mem[78:87] = (31, 24, 27, 3d)
> 900 ns top.master_d : mem[78:87] = (31, 24, 27, 3d)
> 1 us top.master_d : mem[78:87] = (31, 24, 27, 3d)
> 1100 ns top.master_d : mem[78:87] = (31, 24, 27, 3d)
> 1200 ns top.master_d : mem[78:87] = (3c, 41, 46, 5e)
> 1300 ns top.master_d : mem[78:87] = (3c, 41, 46, 5e)
> 1400 ns top.master_d : mem[78:87] = (3c, 41, 46, 5e)
> 1500 ns top.master_d : mem[78:87] = (47, 4d, 53, 6c)
> 1600 ns top.master_d : mem[78:87] = (47, 4d, 53, 6c)
> 1700 ns top.master_d : mem[78:87] = (47, 4d, 53, 6c)
> 1800 ns top.master_d : mem[78:87] = (47, 4d, 53, 6c)
> 1900 ns top.master_d : mem[78:87] = (62, 6a, 60, 7a)
> 2 us top.master_d : mem[78:87] = (62, 6a, 72, 8d)
> 2100 ns top.master_d : mem[78:87] = (62, 6a, 72, 8d)
> 2200 ns top.master_d : mem[78:87] = (62, 6a, 72, 8d)
> 2300 ns top.master_d : mem[78:87] = (6d, 76, 7f, 9b)
> 2400 ns top.master_d : mem[78:87] = (6d, 76, 7f, 9b)
> 2500 ns top.master_d : mem[78:87] = (6d, 76, 7f, 9b)
> 2600 ns top.master_d : mem[78:87] = (78, 82, 8c, a9)
> 2700 ns top.master_d : mem[78:87] = (88, 93, 9e, bc)
> 2800 ns top.master_d : mem[78:87] = (88, 93, 9e, bc)
> 2900 ns top.master_d : mem[78:87] = (88, 93, 9e, bc)
> 3 us top.master_d : mem[78:87] = (93, 9f, ab, ca)
> 3100 ns top.master_d : mem[78:87] = (93, 9f, ab, ca)
> 3200 ns top.master_d : mem[78:87] = (93, 9f, ab, ca)
> 3300 ns top.master_d : mem[78:87] = (9e, ab, b8, d8)
> 3400 ns top.master_d : mem[78:87] = (ae, ab, b8, d8)
> 3500 ns top.master_d : mem[78:87] = (ae, bc, ca, eb)
> 3600 ns top.master_d : mem[78:87] = (ae, bc, ca, eb)
> 3700 ns top.master_d : mem[78:87] = (b9, c8, d7, f9)
> 3800 ns top.master_d : mem[78:87] = (b9, c8, d7, f9)
> 3900 ns top.master_d : mem[78:87] = (b9, c8, d7, f9)
> 4 us top.master_d : mem[78:87] = (c4, d4, d7, f9)
> 4100 ns top.master_d : mem[78:87] = (c4, d4, e4, 107)
> 4200 ns top.master_d : mem[78:87] = (d4, e5, f6, 107)
> 4300 ns top.master_d : mem[78:87] = (d4, e5, f6, 11a)
> 4400 ns top.master_d : mem[78:87] = (df, f1, 103, 128)
> 4500 ns top.master_d : mem[78:87] = (df, f1, 103, 128)
> 4600 ns top.master_d : mem[78:87] = (df, f1, 103, 128)
> 4700 ns top.master_d : mem[78:87] = (df, f1, 103, 128)
> 4800 ns top.master_d : mem[78:87] = (ea, fd, 110, 136)
> 4900 ns top.master_d : mem[78:87] = (fa, fd, 110, 136)
> 5 us top.master_d : mem[78:87] = (fa, 10e, 122, 149)
> 5100 ns top.master_d : mem[78:87] = (105, 11a, 12f, 157)
> 5200 ns top.master_d : mem[78:87] = (105, 11a, 12f, 157)
> 5300 ns top.master_d : mem[78:87] = (105, 11a, 12f, 157)
> 5400 ns top.master_d : mem[78:87] = (105, 11a, 12f, 157)
> 5500 ns top.master_d : mem[78:87] = (110, 126, 13c, 165)
> 5600 ns top.master_d : mem[78:87] = (110, 126, 13c, 165)
> 5700 ns top.master_d : mem[78:87] = (120, 137, 14e, 165)
> 5800 ns top.master_d : mem[78:87] = (12b, 143, 14e, 178)
> 5900 ns top.master_d : mem[78:87] = (12b, 143, 15b, 186)
> 6 us top.master_d : mem[78:87] = (12b, 143, 15b, 186)
> 6100 ns top.master_d : mem[78:87] = (12b, 143, 15b, 186)
> 6200 ns top.master_d : mem[78:87] = (136, 14f, 168, 194)
> 6300 ns top.master_d : mem[78:87] = (136, 14f, 168, 194)
> 6400 ns top.master_d : mem[78:87] = (136, 14f, 168, 194)
> 6500 ns top.master_d : mem[78:87] = (146, 160, 17a, 1a7)
> 6600 ns top.master_d : mem[78:87] = (151, 16c, 187, 1b5)
> 6700 ns top.master_d : mem[78:87] = (151, 16c, 187, 1b5)
> 6800 ns top.master_d : mem[78:87] = (151, 16c, 187, 1b5)
> 6900 ns top.master_d : mem[78:87] = (15c, 178, 194, 1c3)
> 7 us top.master_d : mem[78:87] = (15c, 178, 194, 1c3)
> 7100 ns top.master_d : mem[78:87] = (15c, 178, 194, 1c3)
> 7200 ns top.master_d : mem[78:87] = (16c, 189, 194, 1c3)
> 7300 ns top.master_d : mem[78:87] = (177, 195, 1a1, 1e4)
> 7400 ns top.master_d : mem[78:87] = (177, 195, 1a1, 1e4)
> 7500 ns top.master_d : mem[78:87] = (177, 195, 1a1, 1e4)
> 7600 ns top.master_d : mem[78:87] = (182, 1a1, 1ae, 1f2)
> 7700 ns top.master_d : mem[78:87] = (182, 1a1, 1ae, 1f2)
> 7800 ns top.master_d : mem[78:87] = (182, 1a1, 1ae, 1f2)
> 7900 ns top.master_d : mem[78:87] = (182, 1a1, 1ae, 1f2)
> 8 us top.master_d : mem[78:87] = (18d, 1ad, 1cd, 213)
> 8100 ns top.master_d : mem[78:87] = (18d, 1ad, 1cd, 213)
> 8200 ns top.master_d : mem[78:87] = (18d, 1ad, 1cd, 213)
> 8300 ns top.master_d : mem[78:87] = (18d, 1ad, 1cd, 213)
> 8400 ns top.master_d : mem[78:87] = (198, 1b9, 1da, 221)
> 8500 ns top.master_d : mem[78:87] = (198, 1b9, 1da, 221)
> 8600 ns top.master_d : mem[78:87] = (198, 1b9, 1da, 221)
> 8700 ns top.master_d : mem[78:87] = (1b3, 1c5, 1e7, 22f)
> 8800 ns top.master_d : mem[78:87] = (1b3, 1d6, 1f9, 242)
> 8900 ns top.master_d : mem[78:87] = (1b3, 1d6, 1f9, 242)
> 9 us top.master_d : mem[78:87] = (1b3, 1d6, 1f9, 242)
> 9100 ns top.master_d : mem[78:87] = (1be, 1e2, 206, 250)
> 9200 ns top.master_d : mem[78:87] = (1be, 1e2, 206, 250)
> 9300 ns top.master_d : mem[78:87] = (1be, 1e2, 206, 250)
> 9400 ns top.master_d : mem[78:87] = (1c9, 1ee, 213, 25e)
> 9500 ns top.master_d : mem[78:87] = (1d9, 1ff, 225, 25e)
> 9600 ns top.master_d : mem[78:87] = (1d9, 1ff, 225, 271)
> 9700 ns top.master_d : mem[78:87] = (1d9, 1ff, 225, 271)
> 9800 ns top.master_d : mem[78:87] = (1e4, 20b, 232, 27f)
> 9900 ns top.master_d : mem[78:87] = (1e4, 20b, 232, 27f)
FAIL: simple_bus/test.sh
SystemC 2.3.1-Accellera --- May 19 2015 17:31:07
Copyright © 1996-2014 by all Contributors,
ALL RIGHTS RESERVED
PASS: simple_fifo/test.sh
SystemC 2.3.1-Accellera --- May 19 2015 17:31:07
Copyright © 1996-2014 by all Contributors,
ALL RIGHTS RESERVED
.
.
.
.
.
=============================================================
1 of 21 tests failed
Please report to http://forums.accellera.org/forum/9-systemc/
=============================================================
Makefile:2684: recipe for target 'check-TESTS' failed
make[3]: *** [check-TESTS] Error 1
make[3]: Leaving directory '/cygdrive/d/projects/research/systemc/systemc-2.3.1/systemc-2.3.1/objdir/examples/sysc'
Makefile:2807: recipe for target 'check-am' failed
make[2]: *** [check-am] Error 2
make[2]: Leaving directory '/cygdrive/d/projects/research/systemc/systemc-2.3.1/systemc-2.3.1/objdir/examples/sysc'
Makefile:357: recipe for target 'check-recursive' failed
make[1]: *** [check-recursive] Error 1
make[1]: Leaving directory '/cygdrive/d/projects/research/systemc/systemc-2.3.1/systemc-2.3.1/objdir/examples'
Makefile:434: recipe for target 'check-recursive' failed
make: *** [check-recursive] Error 1
sbanda@sbanda-01 /cygdrive/d/projects/research/systemc/systemc-2.3.1/systemc-2.3.1/objdir
The time at which a packet is generated is stored in the header of the packet. The header allocates only 32 bits for this timestamp.
For any variable of type sc_time T_start, T_start.to_default_time_unit() will return the number of clock cycles if default time unit is configured to (CLK_PERIOD, SC_NS).
The question here is how to convert sc_time values to 32 bits unsigned integer without large loss of precision.
At the producer side this piece of code runs each time is generated:
sc_time t_start = sc_time_stamp(); double magnitude = t_start.to_default_time_unit(); // number of clock cycles since the start of the simulation until this time (is this correct?) unsigned int t_start_u_32 = (unsigned int) std::round(magnitude); // possible loss of precision if magnitude is too large to be presented in 32 bits // store t_start_u_32 in the correspondent packet header field.
At the consumer side (an arbiter that selects packets depending on their age)
double t_start_ret = t_start_u_32 * CLK_PERIOD; sc_time t_start(t_start_ret, SC_NS); sc_time packet_age = sc_time_stamp() - t_start;
Is there any good way to manipulate sc_time variables, default time unit, round/cast operations without loosing precision under the constraint of 32 bits?
I am fairly new to SystemC and am looking for a better way to solve my problem.
In my simulation, I have a set of "resources". I also have a process that accepts requests (using a sc_fifo) and if there is an available resource, farms it out to that resource. The resource "works" on the request for a set of time, then gives it back to the dispatcher. The thing is, for the simulation, the "resource" doesn't actually have to do any work, I just need it to delay for a set amount of time (the time can be different per request).
A way to do this is have each resource be a process. The dispatcher would send the request to the resource, which would wait the required time, then send the request back. In this way the dispatcher would do nb_read on each response sc_fifo and could do a wait on all sc_fifo written events. The problem is this seems like a lot of overhead just to have something delay and then tell the dispatcher the delay is done.
I was looking at the sc_event, and have each resource just be an event. However, you can't determine which event triggered.
So, is there a lightweight way to have my "resources" just wait and then notify my dispatcher when the time has expired, and allow my dispatcher to have multiple of these outstanding and know which one triggered, without making each resource a process?
Thanks.
Hi
I have two modules and they look as follows:
class Derived: public Base,public sc_module
{
...
....
...
Derived(sc_module_name name):sc_module(name){}
};
SC_MODULE(Mysystem)
{
....
.....
SC_CTOR(Mysystem)
{}
};
int sc_main(...)
{
Mysystem MS("mine");
Derived D("derived");
sc_start();
}
I get error:
<E533> module name stack is empty : did you forget to add a parameter to your module constructor?
Why it is showing this error though i provide a module name for "Derived"class??
Note: I ran without having "derived" as the Systemc module and it worked. but, it shows an eror otherwise.
Hi all
I am trying to build a Statemachinefor different tasks that is given as input:
To be more specific, i have different states like Not_ready, ready, running which would do some operations and advance the time respectively
I have something like this:
class StateMachine: public sc_module
{
enum state {NotREAdy, ready,..}
sc_out<bool> out;
void perform
{
switch (state)
{
case Not_ready: ... Do something and update state value to "ready"
case Ready : Do something and update state value to "running"
case Rnning : do some calculation and wait for event
}
out.write(true); // send output to timer module
}
//I have a constructor lik this
StateMachine(sc-module_name name, ......): sc_module(name)
{..
sensitive < Event;
}
};
SC_MODULE(Timer)
{
sc_in<bool> timeIn;
void time()
{
Event.notify(20,SC_NS);
}
SC_CTOR(Timer)
{
senstivity << TimeIn;
SC_METHOD(time);
}
};
main()
{
// I am creating two instances of StateMAchine for TaskA and taskB
StateMachine *M1 = new StateMachine(TaskA, .....);
Statemachine*M2 = new Statemachine(Taskb,.......);
Now when I try to bind the ports, I get error of multple drivers from Statemachine (E115)
How to use vector of ports here with type bool from StateMachine and how to bind it with the port of Timer module??
Hey there
We've developed a small simulation framework using SystemC to allow
simulation of MPEG or DVB transport stream decoding.
It is able to simulate the complete chain: receive -> demultiplex ->
decode -> display (both for audio and/or video) and can be used to
e.g. simulate behaviour based on bitrate or buffering behaviour etc.
We decided to publish the framework and a basic 'ideal' pipeline
(ideal as per MPEG-2 specs) as Open Source under the MIT license.
You can find the framework in our GitHub repository:
https://github.com/Digisoft-tv/TSSim
Any feedback welcome!
Andreas
I start to learn SystemC and SCV. But I don't have much experience on complex Makefile as the one provided in the install package by SCV.
It is too hard for me to understand who the files are really compiled.
I am not sure if any one can provide simple Makefile template (Only Linux platform is OK).
Thanks.
Hi,
I am trying to use SC_FIXED in a UVM ML environment, but the uvm_packer.h doesn't support sc_fixed.
virtual uvm_packer& operator << (bool a); virtual uvm_packer& operator << (char a); virtual uvm_packer& operator << (unsigned char a); virtual uvm_packer& operator << (short a); virtual uvm_packer& operator << (unsigned short a); virtual uvm_packer& operator << (int a); virtual uvm_packer& operator << (unsigned int a); virtual uvm_packer& operator << (long a); virtual uvm_packer& operator << (unsigned long a); virtual uvm_packer& operator << (long long a); virtual uvm_packer& operator << (unsigned long long a); virtual uvm_packer& operator << (std::string a); virtual uvm_packer& operator << (const char*); virtual uvm_packer& operator << (uvm_object* a); virtual uvm_packer& operator << (const uvm_object& a); virtual uvm_packer& operator << (const sc_logic& a); virtual uvm_packer& operator << (const sc_bv_base& a); virtual uvm_packer& operator << (const sc_lv_base& a); virtual uvm_packer& operator << (const sc_int_base& a); virtual uvm_packer& operator << (const sc_uint_base& a); virtual uvm_packer& operator << (const sc_signed& a); virtual uvm_packer& operator << (const sc_unsigned& a); template <class T>
Any idea how to solve it?
Thanks
Hallo,
I have a SC_THREAD which has a dynamic synchronization.
I use a sc_event_or_list as the wait-function argument.
void notifyForGeneratedOutPix(void)
{
using namespace std;
while (true)
{
sc_core::wait( m_outPixEvOrList );
//I'd like to do something like this:
for(auto event : m_outPixEvOrList)
{
if(event.isNotified())
{
cout << "@ " << setw(5) << sc_core::sc_time_stamp();
cout << " | delta cycle: " << setw(5) << sc_core::sc_delta_count();
cout << "Written values from ";
this->dump(cout);
cout << endl;
cout << "value: ";
dumpOutPixel(event); //map access with event as key
}
else continue;
}
}
The events synchronize a method where I need to know which event is notified and has resumed the thread process.
I haven't found a method or function to check an event if it is notified or not. The event class have this enumaration
enum notify_t { NONE, DELTA, TIMED };
but I haven't found something to check that flag.
Is their any way to find out if a event is notified or not?
Thx
*andre*
What is SystemC ? Roughly I think it's a language or more specifically a library useful to create software representation (not synthesizable) of an hardware at an abstarction level higher than RTL (- which is synthesizable).
Please correct me if I am wrong, Also help me with some standardize definition.
What is architectural exploration ? And How SystemC and TLM is useful for it ?
If someone working in a systemC domain, could they classify themselves as a software engineer ? Where does it classify ? Which is more appropriate semiconductor industory , EDA or ESL domain ?
How someone working in systemC explains their Job to someone non-technical person ?
PS: If this question is not appropriate for this forum, then please help me with some details where I could find my answers. I believe these questions must be answered before someone starts learning it.
Hi,
I have a complex design that consists of multiple static and dynamic (spawned) process. I am getting a segmentation fault in sc_core::sc_process_b::semantics function at run time (probably at time when the method is to be invoked). The back trace is as follows.
#0 0x00000000006a3395 in sc_core::sc_process_b::semantics (this=0x1ac81f0) at <Local Installation Path>/systemc-src_2.3.0/src/sysc/kernel/sc_process.h:669
#1 0x00000000006a395f in sc_core::sc_method_process::run_process (this=0x1ac81f0) at <Local Installation Path>/systemc-src_2.3.0/src/sysc/kernel/sc_method_process.h:300
#2 0x00000000006a4a83 in sc_core::sc_simcontext::crunch (this=0xa2d430, once=false) at <Local Installation Path>/systemc-src_2.3.0/src/sysc/kernel/sc_simcontext.cpp:488
#3 0x00000000006a18cc in sc_core::sc_simcontext::simulate (this=0xa2d430, duration=...) at <Local Installation Path>/systemc-src_2.3.0/src/sysc/kernel/sc_simcontext.cpp:890
#4 0x00000000006a2e0a in sc_core::sc_start (duration=..., p=sc_core::SC_RUN_TO_TIME) at <Local Installation Path>/systemc-src_2.3.0/src/sysc/kernel/sc_simcontext.cpp:1583
#5 0x0000000000436c75 in sc_core::sc_start (duration=1000, unit=sc_core::SC_NS, p=sc_core::SC_RUN_TO_TIME) at <Local Installation Path>/systemc-install_2.3.0/include/sysc/kernel/sc_simcontext.h:118
#6 0x00000000004358b5 in sc_main (argc=3, argv=0xa3cdb0) at mnoc_746_main.cpp:50
#7 0x000000000068d366 in sc_core::sc_elab_and_sim (argc=3, argv=0x7fffffff7fa8) at <Local Installation Path>/systemc-src_2.3.0/src/sysc/kernel/sc_main_main.cpp:81
#8 0x000000000068d264 in main (argc=3, argv=0x7fffffff7fa8) at <Local Installation Path>/systemc-src_2.3.0/src/sysc/kernel/sc_main.cpp:34
Any idea of root cause? I could not share the design due to its complexity and too many files
Thanks for your help
Regards,
Dinesh.
Hi
I want to design basic computer with systemc and I faced a problem in my code.
The common bus of yhe basic computer is 16 bit and the address register is 12 bit. When i instantiate address register i don’t know how to connect 12 bit to 16 bit.
AR = new reg12bit ("AR");
(*AR) (inc_ar,ld_ar,clr_ar,bus,ar2buf,clk);
in the above Piece code the output of my register is 12 bit and the bus is 16 bit.
my idea is i use .range() but .range() just used for variables not ports or signals.
please help me.
Hi
i define this signals
sc_signal< sc_lv <8> > ctrl; sc_signal< sc_bit> ctrl_ac;
and i want to assign bit 0 ctrl to ctrl_ac but i dont no how i can do it
ctrl_ac = ctrl[0];
please help me