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Array of Ports

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Hi all,

 

I have a following design:

 

 

I have created a the following Module (in SystemC)

 

Task Module: (Thread)

 

This module gets the load of each task, calculate the remaining time, stores the remaining Time in a global "list" called "ActivationTimings" and sends a signal to Timer Module

 

Timer Module

 

This Module recieves signal from all the task and choose the minimum value from the "ActivationTiming"and advances the Time through event. And the Task Module is sensitive to the event

 

The above things happens till the remaining times of all tasks are zero.

 

 

Since I need to resue the code, I used Array of ports to communicate. My elaboration would look as follows:

 

 

{

Task *A = new Task("Module Name", .....Task Parameters like speed, load.....);

Task *B = new Task("Module Name"..... T);

 

sc_signal<bool> connect[2];

 

 

A->outputTask(connect[0]);       // outTask is the output port of "Task" Module

B->outputTask(connect[1]);

 

 

 

Timer T("Timer");

 

for(int i=0;i<2;i++)

{

 

T.InputTimer[i](connect[i]);    // Using Array of Ports(InputTimer[1]) in Timer Module

 

}

 

sc_start();

}

 

 

 

 

The code works perfectly. but, when i am trying to run the simulation for several iterations,

 

like,

 

for(int i=0;i<100;i++)

{

sc_start(...);

}

 

 

the simulation time gets degraded .

 

Is array of ports reason for this slowdown?? And If so, Why?

 

 

 

 

 

Thanks

 

 

 


systemc softwares features

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Hi

i study about softwares that suport systemc in simuation or synthesis. for example c to silicon compiler from cadene. but when i study datasheet of these softwares ,i cant understand some of the features that in these datasheets. i searching the document that explain this features very good but i cant find it. 
please help

Instantiating array of submodules using sc_vector when submodule constructor has more than one arguments

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Hello,

 

I've been trying to instantiate (if I'm not mistaken) an array of submodules that were created using sc_vector. So far, I've followed the recommendations for using custom creator functions, but I'm kind of lost at how to actually make it work. Especially with sc_bind, which keeps returning me errors.

 

The module master houses an array of ports that will be connected to a corresponding number of slaves. Order of connection does not matter.

 

I'm using MSVC++ 10.

 

The code is as follows:

class top : public sc_module {

	//Submodule declarations
	master master_i;
	sc_vector<slave> slave_i;

	public:

	// Constructor
	top( sc_module_name module_name , int k ) :
	sc_module( module_name ) , master_i("master"), slave_i("slave") {

		slave_i.init(N_SLAVE, sc_bind(&top::create_slave, this, sc_unnamed::_1, sc_unnamed::_2)("slave",k));
		
		sc_assemble_vector(slave_i, &slave::target_port).bind(master_i.initiator_port);

	}

The creator function, which is a member of the class top, is as follows:

static slave* top::create_slave(const char* name, size_t idx) {
		
		slave* s = new slave(name,1); // Hardcoding not intended; it's just to get it to
                                              //  compile
		return s;

	}

slave class constructor prototype: 

slave( sc_module_name module_name , int k );

Errors that I have so far:

1>c:\systemc\systemc-2.3.1\src\sysc\packages\boost\bind.hpp(63): error C2825: 'F': must be a class or namespace when followed by '::'
1>          c:\systemc\systemc-2.3.1\src\sysc\packages\boost\bind\bind_template.hpp(15) : see reference to class template instantiation 'sc_boost::_bi::result_traits<R,F>' being compiled
1>          with
1>          [
1>              R=sc_boost::_bi::unspecified,
1>              F=slave *(__cdecl *)(const char *,size_t)
1>          ]
1>          c:\users\khairul\dropbox\cours\systemc\examples\source\11\master_slave\top.h(32) : see reference to class template instantiation 'sc_boost::_bi::bind_t<R,F,L>' being compiled
1>          with
1>          [
1>              R=sc_boost::_bi::unspecified,
1>              F=slave *(__cdecl *)(const char *,size_t),
1>              L=sc_boost::_bi::list3<sc_boost::_bi::value<top *>,sc_boost::arg<1>,sc_boost::arg<2>>
1>          ]

Any ideas?

 

Thanks,

using tagged socket

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Hello all,

 

i am using tlm socket and declared as following

tlm_utils::simple_initiator_socket_tagged<current_model> initiator_socket[2];

 

// in construcot

               initiator_socket[0] = new tlm_utils::simple_initiator_socket_tagged<current_model>("socket0");
               initiator_socket[1] = new tlm_utils::simple_initiator_socket_tagged<current_model>("socket1");

 

error: no match for ‘operator=’ (operand types are ‘tlm_utils::simple_initiator_socket_tagged<current_model<unsigned int, 32u>, 32u, tlm::tlm_base_protocol_types>’ and ‘tlm_utils::simple_initiator_socket_tagged<current_model<unsigned int, 32u>, 32u, tlm::tlm_base_protocol_types>*’)
initiator_socket[0] = new tlm_utils::simple_initiator_socket_tagged<current_model>(txt);

 

Shared Variables in SC_THREAD

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Hi all

 

If I have something like follows:

SC_MODULE(Test)

{

...

 

int t1; // Want this variable to be shared

 

void  tesst()

{

 

t1 = t1 +2;

 

}

 

SC_CTOR(Test)

{

SC_THREAD(tesst)

}

 

 

 

And then I create two instances of Test as 

 

Test *t1 =  new ....;

Test *t2 = new ...

 

 

 

 

Then , how can make the varible "t1"shared by both the instances/ threads?

 

 

In other words, I want this variable to be updated by both the threads.

 

 

 

 

 

 

 

 

Thanks

sc_report_info

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I use SystemC models in a UVM environment, and am recently updating the reporting for the SysC model from cout -> SC_REPORT_INFO(MSGID,str);

 

Simple question: how do I use this to return a value along with a message?  Example, SC_REPORT_INFO(MSGID,fcn("The value is=%0d", myint));

 

 

How to optimise this code?

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Hello,

I've recently completed a design but I'm not convinced that it is an optimal one.

How would you modify this to give optimal speed?

EDIT: I've attached it in a file.

Attached Files

wait() - performance Bottleneck

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Hi all

 

 

I have a project where I create SystemC threads and they perform co operatively with wait(event) statement in two places of  the algorithm.

 

The algorithm works fine. But, the problem is when I run the algorithm for multiple times (like 1000 times), I could see a lot of time is consumed by the wait() statements.

 

(I used a Visual Studio Community 2013 profiler)

 

 

 

Is it a performance bottleneck if it runs for many times??

 

 

Sorry, if my question is abstract. I am happy to elaborate further if my question is not clear

 

 

 

thanks

 

 

 


Unable to install SystemC library on my system

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Hello.

I have a Windows 7 32-bit system.
I have been trying to install the SystemC library on "Visual Studio C++ 2010 Express" but am getting the error shown in the images I uploaded.
Why is the vcproj file not getting converted? I don't understand how to make the changes the Conversion Report is suggesting.

Please help me with this problem.

Attached Thumbnails

  • systemc.JPG
  • systemc1.JPG

how to model registers

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Hi, I have an assignment in which I should model an adc. This adc has some 32 bit registers that must be accessed from a header file in order to write or read data from the adc. I have tried doing this by using a pointer, but I get a segmentation fault when accessing it in my program. I know that it is not possible to have custom address in c++ that you can write to. In this case, how it is possible to model such register in systemC?

 

for example in registers.h I have the following

#define control_register 0x40038000

 

 

and I try to write in some function of a systemc module

*((int *) control_register) = 2;

 

So, obviously I get the segmentation fault

 

SystemC threads stack overflow?

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My top-level is a NoC consists of a Network-On-Chip with a grid of 15*15 nodes (Router+PE).

Been trying to simulate it in different machines/configurations but kept stopping at different times of the simulation. Can't see what causes the problem and hence I am stack.

1) Running only SystemC / C++ executable (output of the compiler) in a LSF cluster. Simulation runs normally with expected output then it stops at the 55000ish cycle (cycle accurate model) with this error message:

noc_exe: ../../../../src/sysc/kernel/sc_cor_qt.cpp:107: virtual void sc_core::sc_cor_qt::stack_protect(bool): Assertion `ret == 0' failed.
/home/#######/.lsbatch/1438183854.772657: line 8: 15547 Aborted                 (core dumped) ./noc_exe

2) Running with Cadence irun command in a LSF cluster. The simulation was heaps of times slower but managed to reach 100 000ish cycles before generating this error message:

Simulation interrupted at 1025080 NS + 0                              
ncsim> ncsim: *W,NCTERM: Simulation received SIGTERM signal from process 22268, user id 0 (/env/seki/app/lsf/8.0/etc/sbatchd).                                                                                                                
make: *** [run] Error 15

I have investigated the error NCTERM with nchelp and got:

nchelp: 14.20-s010: (c) Copyright 1995-2015 Cadence Design Systems, Inc.
ncsim/NCTERM =
        A SIGTERM signal was received by the running simulation. This signal
        may have been issued due to various reasons:

          * sent by the user using the kill command
          * machine on which the job was running went down
          * sent by LSF (Load Sharing Facility) to enforce certain user
            specified job control limits (memory, CPU, swap, etc.)

I had a little doubt that the stack size might not be enough for my threads. The outputs from 1) and 2) took place even after I tried to increase the stack size.

In 2), it is enough to add the

-SC_THREAD_STACKSIZE 0x80000

switch to irun command.

In 1), I had to go to every registration of thread in my constructors and append it with another line:

SC_THREAD(controller_thread);
set_stack_size(NOC_THREAD_STACK_SIZE); // 0x80000

I'd appreciate any prompt reply :)

 

When I run the same test with a smaller number of nodes, the issue does not occur.

Building A Third Party Application which uses TLM 2.0

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Hi,

 

I am trying to build 32-bit application which uses SystemC in it on my 64-bit Ubuntu. When running the make file it gives an error because it cannot find "lib-linux/libsystemc.a"

 

And that is because I am using a 64-bit linux. (So I have "lib-linux64/libsystemc.a" instead!)

 

I suppose the make file is expecting 32-bit version of the static library. If that is the case, the question is how can I install the 32-bit version of the SystemC library on my machine.

 

Here's the make command and its output:

hooman@hooman-ThinkPad-S540:~/OVP/systemc_example/SystemC_TLM2.0/platform_cpp$ make -f /home/hooman/OVP/Imperas.20150205/ImperasLib/buildutils/Makefile.TLM.platform
# Compiling Build/Linux32/sys/tlmMemory.o
# Compiling Build/Linux32/sys/tlmMmc.o
# Compiling Build/Linux32/sys/tlmPeripheral.o
# Compiling Build/Linux32/sys/tlmPlatform.o
# Compiling Build/Linux32/sys/tlmProcessor.o
# Compiling Build/Linux32/usr/platform.o
# Linking platform.Linux32.exe
g++: error: /usr/local/systemc230/lib-linux/libsystemc.a: No such file or directory
make: *** [platform.Linux32.exe] Error 1

How should I design multiple writers?

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I am trying to design a simple system in SystemC. Its just for educational purposes.

 

Basically, I have a module Random, that generates random numbers, and a module Square, that takes a number and give back its square.

 

Its ok when I have only 1 object of each module active. But how sould I do it if I have 2 instances of Random trying to use 1 instance of Square?

 

I was trying to write in Square just 1 port in and 1 port out. But it is not allowed to have a FIFO with multiple writers. Im quite confused on how I should implement this. My current idea (which I feel is not right) is to write my own channel (that will have multiple primitive channels inside) and will work to join all data received from this primitives.

 

Thanks

memory definition

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Hi
is this memory definition is true?
SC_MODULE(mem16)
{
  sc_in <sc_lv <16> > in1;
  sc_out <sc_lv <16> > out1;
  sc_in <sc_lv <12> > addr;
  sc_in <bool> ld;
  sc_in_clk clk;
  int i;
  void write_data();
  sc_lv <16> ram_data[4096];
  SC_CTOR(mem16)
  {
    SC_METHOD(write_data);
    sensitive << addr << ld << in1 << clk ;
	//memory initialization
	ram_data[0]="0000000000000001";
	ram_data[1]="0000000000000011";
	ram_data[2]="0000000000000111";
	ram_data[3]="0000000000001111";
	ram_data[4]="0000000000011111";
	ram_data[5]="0000000000111111";
	ram_data[6]="0000000001111111";
    //for (i=7; i++; i<4095)
    //ram_data[i] = 0;

  }
};
void mem16::write_data()
{
	
  out1 = ram_data[addr.read().to_int()];
  if(clk){
  if (ld) {
    ram_data[addr.read().to_int()] = in1;
  }
	}
}

 

a problem with systemc VCD veiw

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Hi

i write this sample code

in this code i connect two register

i want to trace bus_out signal that is between two register with VCD view

but in VCD view the value of bus_out signal is xxxx

while bus_out must be value!

the image of VCD is attached

// mahbod
#include "systemc.h"

// define reg 16 bit
SC_MODULE (reg16bit) {

sc_in <bool> inc,ld,clr;
sc_in <sc_lv <16> > in16;
sc_out <sc_lv <16> > out16;
sc_in <bool> clk;
void reg_func ();
SC_CTOR (reg16bit) {
SC_THREAD (reg_func);
sensitive << clk.pos();
}
};
// define reg function
void reg16bit::reg_func ()
{
while (1) {
if (ld) 
  out16 = in16;
if (clr)
  out16 = "0000000000000000";
if(inc)
  out16 = (sc_lv <16>)(out16.read().to_int()+1);
wait ();
}
}
//end define reg 16 bit

// defination data path madule
  SC_MODULE(data_path) {
 
    sc_in_clk clk;
    sc_in < sc_lv <16> >  inp;
	sc_in < bool > ld_ac;
	sc_in < bool > inc_ac;
	sc_in < bool > clr_ac; 
	sc_in < bool > ld_inp;
	sc_in < bool > inc_inp;
	sc_in < bool > clr_inp; 
	sc_out < sc_lv <16> > outp; 
	sc_out < sc_lv <16> > bus_out; 
    sc_signal< sc_lv <16> > bus;

reg16bit *AC;
reg16bit *INP;
  
 void process() {
	bus_out = bus.read();
	}

    SC_CTOR(data_path) {

		AC = new reg16bit ("AC");
		AC->inc(inc_ac);
		AC->ld(ld_ac);
		AC->clr(clr_ac);
		AC->in16(bus);
		AC->out16(outp);
		AC->clk(clk);
 
        INP = new reg16bit ("INP");
		INP->inc(inc_inp);
		INP->ld(ld_inp);
		INP->clr(clr_inp);
		INP->in16(inp);
		INP->out16(bus);
		INP->clk(clk); 
    }
	
};

SC_MODULE(test_bench) {
	sc_in_clk clk;
    sc_out < sc_lv <16> > inp;

	sc_out < bool > ld_ac;
	sc_out < bool > inc_ac;
	sc_out < bool > clr_ac;

	sc_out < bool > ld_inp;
	sc_out < bool > inc_inp;
	sc_out < bool > clr_inp;

	sc_in < sc_lv <16> > outp;
	sc_in < sc_lv <16> > bus_out; 
	void process()
	{
		while(1) {

			inp = (sc_lv <16>) "0000000000000110"; 
			wait();
			ld_inp = (bool) 1;
			wait();
			ld_inp = (bool) 0;
			wait();
			ld_ac = (bool) 1;
			wait();
			ld_ac = (bool) 0;
			wait();
			inc_ac = (bool) 1;
			wait();
			inc_ac = (bool) 0;
			wait();
		}
	}

	SC_CTOR(test_bench) {
		SC_CTHREAD(process, clk.pos() );
	}
};


int sc_main(int argc, char* argv[]) {
	sc_clock clk;
    sc_signal < sc_lv <16> > inp;
	sc_signal < bool > ld_ac;
	sc_signal < bool > inc_ac;
	sc_signal < bool > clr_ac;
	sc_signal < bool > ld_inp;
	sc_signal < bool > inc_inp;
	sc_signal < bool > clr_inp;
	sc_signal < sc_lv <16> > outp;
	sc_signal < sc_lv <16> > bus_out;
	data_path *data_p;
	test_bench *tb;


	data_p = new data_path("data_p");
	data_p->clk(clk);
	data_p->inp(inp);
	data_p->ld_ac(ld_ac);
	data_p->inc_ac(inc_ac);
	data_p->clr_ac(clr_ac);
	data_p->ld_inp(ld_inp);
	data_p->inc_inp(inc_inp);
	data_p->clr_inp(clr_inp);
	data_p->outp(outp);
	data_p->bus_out(bus_out);
	

    tb = new test_bench ("testBench");
	tb->clk(clk);
	tb->inp(inp);
	tb->ld_ac(ld_ac);
	tb->inc_ac(inc_ac);
	tb->clr_ac(clr_ac);
	tb->ld_inp(ld_inp);
	tb->inc_inp(inc_inp);
	tb->clr_inp(clr_inp);
	tb->outp(outp);
	tb->bus_out(bus_out);

    sc_trace_file *tf;
	tf = sc_create_vcd_trace_file("BufferTraceFile"); // file extension defaults to ".vcd"
	sc_trace(tf,clk,"clk");
	sc_trace(tf,inp,"inp");
	sc_trace(tf,outp,"outp");
	sc_trace(tf,ld_ac,"ld_ac");
    sc_trace(tf,ld_inp,"ld_inp");
	sc_trace(tf,inc_ac,"inc_ac");
	sc_trace(tf,inc_inp,"inc_inp");
	sc_trace(tf,clr_ac,"clr_ac");
	sc_trace(tf,clr_inp,"clr_inp");
	sc_trace(tf,bus_out,"bus_out");	
	sc_start(100);
	sc_close_vcd_trace_file(tf);
	return 0;
}

Attached Thumbnails

  • 222.png

Installation (configure) problem

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Hi!,

I'm trying to install SystemC by following the INSTALL doc instructions.

 

> mkdir objdir

> cd objdir

> setenv CXX g++

> ../configure

../configure: Command not found.

>

 

There is no information about which command is not found. 

 

XTERM_SHELL=/usr/intel/pkgs/tcsh/6.15.00/bin/tcsh

HOSTTYPE=x86_64

MACHTYPE=x86_64-suse-linux

HOSTYPE=x86-64_linux_sles11
VER=sles11
 
Thanks in advance!
 

flow of the signals

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Hi

i want to manage the flow of the out put ports of the main controller (see figure)

for this goal i design a counter and connect it to the decoder

the out put of the decoder is T[0] to T[15]

for example the order of the ports as follow

but this idea is not work

ld_dr.write(T.read()[0]);
ld_ac.write(T.read()[1]);
ld_tr.write(T.read()[2]);
ld_ir.write(T.read()[3]);
ld_pc.write(T.read()[4]);
ld_ar.write(T.read()[5]);
ld_ou.write(T.read()[6]);
ld_inp.write(T.read()[7]);

the code is here

#include "systemc.h"

// define counter
SC_MODULE(counter) {

  sc_in_clk clk;
  sc_in <bool> clear;
  sc_out <sc_lv <4> > dout;
  int countval;

  void onetwothree();
  SC_CTOR(counter)
  {
    SC_METHOD(onetwothree);
    sensitive<<clk.pos();
  }
};
void counter::onetwothree()
{
  if (clear) 
    countval = 0;
    else 
    countval++;
  dout = countval;
}

///////////////////////

//define dec
SC_MODULE (dec_4){
sc_in_clk clk;
sc_in< sc_lv<4> > in_d;
sc_out< sc_lv<16> > out_d;

void process() {
    if (in_d.read() == "0000")
		out_d = "0000000000000001";
    else
    if (in_d.read() == "0001")
        out_d = "0000000000000010";
    else 
    if(in_d.read() =="0010")
        out_d = "0000000000000100";
    else
    if (in_d.read() == "0011")
        out_d = "0000000000001000";
    else
    if (in_d.read() == "0100")
        out_d = "0000000000010000";
    else
    if (in_d.read() == "0101")
        out_d = "0000000000100000";
    else
    if (in_d.read() == "0110")
        out_d = "0000000001000000";
	else
    if (in_d.read() == "0111")
        out_d = "0000000010000000";
    else
	if (in_d.read() == "1000")
        out_d = "0000000100000000";
    else
    if (in_d.read() == "1001")
        out_d = "0000001000000000";
    else 
    if(in_d.read() == "1010")
        out_d = "0000010000000000";
    else
    if (in_d.read() == "1011")
        out_d = "0000100000000000";
    else
    if (in_d.read() == "1100")
        out_d = "0001000000000000";
    else
    if (in_d.read() == "1101")
        out_d = "0010000000000000";
    else
    if (in_d.read() == "1110")
        out_d = "0100000000000000";
	else
    if (in_d.read() == "1111")
        out_d = "1000000000000000";
}
SC_CTOR(dec_4) {
		SC_METHOD(process);
		sensitive<<clk.pos();
	}
};
  //end define module DEC
  
//define controller
SC_MODULE(controller) {
	sc_in_clk clk;
	sc_in < sc_lv <16> > T;
	sc_out < bool > reset_counter;
	sc_out < sc_logic > ld_ac;
	sc_out < sc_logic > ld_dr;
	sc_out < sc_logic > ld_ir;
	sc_out < sc_logic > ld_tr;
	sc_out < sc_logic > ld_pc;
	sc_out < sc_logic > ld_ar;
	sc_out < sc_logic > ld_ou;
	sc_out < sc_logic > ld_inp;
	
	void process()
	{

	ld_dr.write(T.read()[0]);
	ld_ac.write(T.read()[1]);
	ld_tr.write(T.read()[2]);
	ld_ir.write(T.read()[3]);
	ld_pc.write(T.read()[4]);
	ld_ar.write(T.read()[5]);
	ld_ou.write(T.read()[6]);
	ld_inp.write(T.read()[7]);

	}
	SC_CTOR(controller) {
		SC_CTHREAD(process,clk.pos());
	}
};
///////////////////////////////

// define main_controller madul
SC_MODULE(main_controller) {
 
    sc_in_clk clk;
	sc_out < sc_logic > ld_ac;
	sc_out < sc_logic > ld_dr;
	sc_out < sc_logic > ld_ir;
	sc_out < sc_logic > ld_tr;
	sc_out < sc_logic > ld_pc;
	sc_out < sc_logic > ld_ar;
	sc_out < sc_logic > ld_ou;
	sc_out < sc_logic > ld_inp;
	sc_out <sc_lv <4> > count_out;
	sc_out <sc_lv <16> > dec_out;

    sc_signal < sc_lv <16> > T;
	sc_signal < sc_lv <4> > count2dec;
	sc_signal < bool > reset_counter;
	
dec_4 *DEC_2;
counter *COUNT;
controller *CONTROL;
void copier() {

	count_out = count2dec.read();
    dec_out =  T.read();
	}

    SC_CTOR(main_controller) {
		 SC_METHOD(copier);
        sensitive << clk;

		DEC_2 = new dec_4 ("DEC_2");
		DEC_2 -> clk(clk);
		DEC_2 -> in_d(count2dec);
		DEC_2 -> out_d(T);

		COUNT = new counter ("COUNT");
		COUNT -> clk(clk);
		COUNT -> clear(reset_counter);
		COUNT -> dout(count2dec);

		CONTROL = new controller ("CONTROL");
		CONTROL -> clk(clk);
		CONTROL -> T(T);
		CONTROL -> reset_counter(reset_counter);
		CONTROL -> ld_ac(ld_ac);
		CONTROL -> ld_dr(ld_dr);
		CONTROL -> ld_ir(ld_ir);
		CONTROL -> ld_tr(ld_tr);
		CONTROL -> ld_pc(ld_pc);
		CONTROL -> ld_ar(ld_ar);
		CONTROL -> ld_ou(ld_ou);
		CONTROL -> ld_inp(ld_inp);
			
    }
};

SC_MODULE(test_bench) {
	sc_in_clk clk;
	sc_in < sc_logic > ld_ac;
	sc_in < sc_logic > ld_dr;
	sc_in < sc_logic > ld_ir;
	sc_in < sc_logic > ld_tr;
	sc_in < sc_logic > ld_pc;
	sc_in < sc_logic > ld_ar;
	sc_in < sc_logic > ld_ou;
	sc_in < sc_logic > ld_inp;
	//sc_in <sc_lv <16> > count_out;

	sc_in <sc_lv <4> > count_out;
	sc_in <sc_lv <16> > dec_out;

	void process()
	{
	}

	SC_CTOR(test_bench) {
		SC_CTHREAD(process, clk.pos() );
	}
};

int sc_main(int argc, char* argv[]) {

	sc_clock clk;
	sc_signal < sc_logic > ld_ac;
	sc_signal < sc_logic > ld_dr;
	sc_signal < sc_logic > ld_ir;
	sc_signal < sc_logic > ld_tr;
	sc_signal < sc_logic > ld_pc;
	sc_signal < sc_logic > ld_ar;
	sc_signal < sc_logic > ld_ou;
	sc_signal < sc_logic > ld_inp;
	//sc_signal < sc_lv <16> > count_out;

	sc_signal <sc_lv <4> > count_out;
	sc_signal <sc_lv <16> > dec_out;

	
	main_controller *data_p;
	test_bench *tb;

	data_p = new main_controller("data_p");
	data_p->clk(clk);
	data_p->ld_ac(ld_ac);
	data_p->ld_dr(ld_dr);
	data_p->ld_ir(ld_ir);
	data_p->ld_tr(ld_tr);
	data_p->ld_pc(ld_pc);
	data_p->ld_ar(ld_ar);
	data_p->ld_ou(ld_ou);
	data_p->ld_inp(ld_inp);
	//data_p->count_out(count_out);
	data_p->count_out(count_out);
	data_p->dec_out(dec_out);


    tb = new test_bench ("testBench");
	tb->clk(clk);
	tb->ld_ac(ld_ac);
	tb->ld_dr(ld_dr);
	tb->ld_ir(ld_ir);
	tb->ld_tr(ld_tr);
	tb->ld_pc(ld_pc);
	tb->ld_ar(ld_ar);
	tb->ld_ou(ld_ou);
	tb->ld_inp(ld_inp);
//	tb->count_out(count_out);

	tb->count_out(count_out);
	tb->dec_out(dec_out);

	
    sc_trace_file *tf;
	tf = sc_create_vcd_trace_file("BufferTraceFile"); // file extension defaults to ".vcd"

	sc_trace(tf,clk,"clk");

	sc_trace(tf, count_out, "count_out");
	sc_trace(tf, dec_out, "dec_out");

	sc_trace(tf, ld_ac, "ld_ac");
	sc_trace(tf, ld_dr, "ld_dr");
	sc_trace(tf, ld_ir, "ld_ir");
	sc_trace(tf, ld_tr, "ld_tr");
	sc_trace(tf, ld_pc, "ld_pc");
	sc_trace(tf, ld_ar, "ld_ar");
	sc_trace(tf, ld_ou, "ld_ou");
	sc_trace(tf, ld_inp, "ld_inp");

	sc_start(50);
	sc_close_vcd_trace_file(tf);
	return 0;
}





Attached Thumbnails

  • 562.png

SystemC queue

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Hi,

 

Does SystemC support queue like SystemVerilog?

 

I want to create dynamic array in SystemC TLM2.0, can any one suggest a better way to do it?

 

Thanks

Zubin

Preventing a method from triggering more than once in a given cycle

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I'm developing a performance simulator for a hardware unit. The hardware runs at 1GHz and therefore I define a clock cycle as:

sc_time clk(1, SC_NS)

In a specific module requests arrive to the input port, triggering a method that places them into a request buffer. At some point requests that are ready for processing are moved out from the request buffer and placed into another buffer. The overall design would look like:

void Receive() {
  auto x = input.read();
  buffer_.push_back(x);
  process_buffer_event_.notify(clk);
}

void ProcessBuffer() {
  for (auto it = begin(buffer_); it != end(buffer_); ++it) {
    if (process_entry(*it)) { // returns true if a request was successfully moved to the second buffer
      buffer_.erase(it);
      break; // only one request can be processed per cycle
    }
  }

  if (!buffer_.empty())
    process_buffer_event_.notify(clk);
}

So, ProcessBuffer will trigger either when a new request arrives or when a request is processed and there are still requests in the buffer. However, there is another case when ProcessBuffer should trigger. In the module there are some resources that can be either in use or idle. Whenever a resource becomes idle, ProcessBuffer must immediately trigger (without waiting until the next cycle):

void ReleaseResources() {
  bool any_released = false;
  for (auto& r : resources_)
    any_released = r->try_to_release() || any_released;

  if (any_released)
    process_buffer_event_.notify(SC_ZERO_TIME);
}

However, because of this piece of code, ProcessBuffer now may trigger twice in a given cycle (in the same nanosecond). I suspect it is related to using SC_ZERO_TIME, but I'm not really sure. This creates an issue since now two requests might be moved into the second buffer. I suppose I could guard against executing ProcessBuffer twice by doing something like:

void ProcessBuffer() {
  if (sc_time_stamp() == last_time_processed)
    return;
  
  last_time_processed = sc_time_stamp();

  for (auto it = begin(buffer_); it != end(buffer_); ++it) {
    if (process_entry(*it)) {
      buffer_.erase(it);
      break; // only one request can be processed per cycle
    }
  }

  if (!buffer_.empty())
    process_buffer_event_.notify(clk);
}

But I was just wondering whether there is some mechanism in SystemC to properly prevent a method from triggering more than once.

wait()

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are wait() capable to synthesis in systemc?

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