Hi All

I see immediate notification is not possible with sc_event_queue objects.

Is there some specific reason for this.

Thanks

I have used Modelsim to compare simulation results between a C model encapsulated in SystemC to its VHDL implementation, mostly with a GUI, for hardware verification.
 

I am trying to see how SystemC can be used for Software validation and/or regression testing using a SystemC testbench that has software modules, SystemC models, and VHDL HW modules when fidelity is needed. I am assuming the open-source SystemC simulator does not support VHDL natively so a VHDL simulator would be needed like modelsim.
 

What is the best way to use the SystemC open source simulation to make calls to a VHDL simulator like modelsim while reducing the license usage of modelsim?
 

Can you share your experience and lessons learned regarding mixed language sims?
 

Thanks

Paul

Hi Guys

I am getting the segmentation fault with following simple program, which I am not able to figure out why. Can you please help

#include "systemc.h"

class initiator : public sc_module {
    public:
    sc_signal<int> out;
    SC_HAS_PROCESS(initiator);
    initiator(sc_module_name name){
        SC_THREAD(process1);
        SC_THREAD(process2);
    }
    void process1(){
        wait(10,SC_NS);
        out.write(1);
    }
    void process2(){
        wait(1,SC_NS);
        out.write(0);
    }
};

int sc_main(int, char**){
    initiator* initiator_inst = new initiator("initiator");
    sc_start(100, SC_NS);
    return 0;
}

Can you please help.

Thanks

RahulJn

Hi,

I am reciving

Error: (E100) port specified outside of module: port 'port_0' (sc_port_base)
In file: ../../../../src/sysc/communication/sc_port.cpp:231

When I try to bild my systemc simulation. I have written a small example, that reproduce the error on my machine:

main.cpp

#include "systemc.h"
#include "exampleModule.cpp"

int sc_main (int argc, char* argv[])
{

    ExampleModule example("example");
}

exampleModule.cpp

#include "systemc.h"

struct ExampleModule : ::sc_core::sc_module{
public:
    sc_fifo_in<int> out;

    void readData(){

    }

    SC_HAS_PROCESS(ExampleModule);
    ExampleModule( const char* name ): sc_module( sc_module_name(name) )
    {
        cout << "name:" << this->name() << endl;
        SC_THREAD(readData);
    }

};

It looks like the error is in

ExampleModule( const char* name ): sc_module( sc_module_name(name) )

While debuggin this part I get an unexpected jump to sc_port.

When I'm changing the code to

ExampleModule( const char* name ): sc_module( name )

everything is fine. But this is deprecated.

Has anyone a suggestion what im doing wrong?

Regards
 

I have 3 modules in my SystemC Test Bench -

Module 1 which is the test control module Looks like the following-

====================================================================================
#ifndef M_TEST_CONTROL_H
#define M_TEST_CONTROL_H

#include "systemc.h"
///////////////////////////////////////////////////////////
//This is just the test control module
///////////////////////////////////////////////////////////


SC_MODULE(m_test_control)
{


  //declairation of tests control signals
  sc_out<bool> enable_clk;


  SC_CTOR(m_test_control)
    {


      SC_THREAD(module_main);


    }




  void module_main(void);




};


#endif


void m_test_control::module_main(void)
{
  ///////////////////////////////////////////
  //Time 0 initialization
  ///////////////////////////////////////////
  enable_clk.write(0);
  wait(100, SC_NS);
  enable_clk.write(1);
  ///////////////////////////////////////////
  //Main Thread....
  ///////////////////////////////////////////
  //for(; {


    wait(100.00, SC_NS);
    cout<<" Stuck here "<< sc_time_stamp() << endl;
    //}






}

#ifndef M_MULTI_PHASE_CLOCK_GEN_H
#define M_MULTI_PHASE_CLOCK_GEN_H


#include "systemc.h"
///////////////////////////////////////////////////////////
//This module mimics the clock generator for the modulator
///////////////////////////////////////////////////////////


SC_MODULE(m_multi_phase_clock_gen)
{


  sc_out<bool> clk, clk_45, clk_90, clk_135;
  sc_out<bool> clk_180, clk_225, clk_270, clk_315;
  sc_in<bool> enable_clk;


  SC_CTOR(m_multi_phase_clock_gen)
    {


    
      SC_THREAD(module_main);
      //sensitive << enable_clk;




      ///////////////////////////////////////////////////
      //Danger !!!! - Never attempt to initialize ports
      //in constructor !!! We elaborte in this phase !!!
      ///////////////////////////////////////////////////


      //initialize all the phases --NOT !!!!
      //clk.write(0);
      //clk_45.write(0);
      //clk_90.write(0);
      //clk_135.write(0);
      //clk_180.write(0);
      //clk_225.write(0);
      //clk_270.write(0);
      //clk_315.write(0);


    }


  void module_main(void);


};


#endif


void m_multi_phase_clock_gen::module_main(void)
{


  ////////////////////////////////////////////////////
  //Time 0 initialization !!!
  ////////////////////////////////////////////////////
  cout << "Clock Generator Initialized at time " << sc_time_stamp() << endl;
  clk.write(0);
  clk_45.write(0);
  clk_90.write(0);
  clk_135.write(0);
  clk_180.write(0);
  clk_225.write(0);
  clk_270.write(0);
  clk_315.write(0);
  
  wait(1.00, SC_NS);


  ////////////////////////////////////////////////////
  //Main Thread...
  ////////////////////////////////////////////////////
  while(enable_clk.read()){
    
    //generate phase 0
    clk.write(!clk.read());
    wait(1.25, SC_NS);
    
    //generate phase 1
    clk_45.write(!clk_45.read());
    wait(1.25, SC_NS);
    
    //generate phase 2
    clk_90.write(!clk_90.read());      
    wait(1.25, SC_NS);
    
    //generate phase 3
    clk_135.write(!clk_135.read());
    wait(1.25, SC_NS);
    
    //generate phase 4
    clk_180.write(!clk_180.read());
    wait(1.25, SC_NS);
    
    //generate phase 5
    clk_225.write(!clk_225.read());
    wait(1.25, SC_NS);
    
    //generate phase 6
    clk_270.write(!clk_270.read());      
    wait(1.25, SC_NS);
    
    //generate phase 7
    clk_315.write(!clk_315.read());
    wait(1.25, SC_NS);
    
  }
  
  
}

#ifndef M_ANALOG_CORE_H
#define M_ANALOG_CORE_H


#include "systemc.h"
#include "m_multi_phase_clock_gen.h"
//////////////////////////////////////////////////
//This module is the netlist of the Analog Core
//////////////////////////////////////////////////


SC_MODULE(m_analog_core)
{


  //top level I/O
  sc_out<bool> clk, clk_45, clk_90, clk_135;
  sc_out<bool> clk_180, clk_225, clk_270, clk_315;
  sc_in<bool> enable_clk;
  
  //internal modules
  m_multi_phase_clock_gen i_clock_gen;


  SC_CTOR(m_analog_core):
    //in constructor, name all ports, module instantiations and whatever can be named !!!
    i_clock_gen("i_clock_gen"),
    clk("clk"), clk_45("clk_45"), clk_90("clk_90"), clk_135("clk_135"),
    clk_180("clk_180"), clk_225("clk_225"), clk_270("clk_270"), clk_315("clk_315")
    {
      
      i_clock_gen.clk(clk);
      i_clock_gen.clk_45(clk_45);
      i_clock_gen.clk_90(clk_90);
      i_clock_gen.clk_135(clk_135);
      i_clock_gen.clk_180(clk_180);
      i_clock_gen.clk_225(clk_225);
      i_clock_gen.clk_270(clk_270);
      i_clock_gen.clk_315(clk_315);
      i_clock_gen.enable_clk(enable_clk);
     


    }


};




#endif

Module 4 which is the pulse generator module looks line this -

========================================================================================================================

#ifndef M_PULSE_GEN_H
#define M_PULSE_GEN_H


#include "systemc.h"
///////////////////////////////////////////////////////////
//This module is the fractional pulse generator for the modulator
///////////////////////////////////////////////////////////




SC_MODULE(m_pulse_gen)
{
  sc_in <bool> clk, clk_45, clk_90, clk_135;
  sc_in <bool> clk_180, clk_225, clk_270, clk_315;
  sc_out<sc_uint<8> > pulse;




  
  SC_CTOR(m_pulse_gen)
    {
     
      SC_METHOD(module_main);
      sensitive << clk << clk_45 << clk_90 << clk_135;
      sensitive << clk_180 << clk_225 << clk_270 << clk_315;
      
    }
  
  void module_main(void);
  
};


#endif


void m_pulse_gen::module_main(void)
{


  //create a bus form the individual clock bits
  bool c_bus_bits[8];
  unsigned int c_bus;
  
  //create the pulse array
  bool frac_pulse[8];
  


  
  //this will create a bus that is a concatenation of all the 
  //clock phases...
  c_bus_bits[0] = clk;
  c_bus_bits[1] = clk_45;
  c_bus_bits[2] = clk_90;
  c_bus_bits[3] = clk_135;
  c_bus_bits[4] = clk_180;
  c_bus_bits[5] = clk_225;
  c_bus_bits[6] = clk_270;
  c_bus_bits[7] = clk_315;
  
  c_bus = 0;
  for(int ii=0; ii < 8; ii++){
    c_bus = c_bus | (c_bus_bits[ii] << ii);
  }
  
  cout << "Pulse gen activated at time "  
       << sc_time_stamp() 
       << " " 
       << c_bus_bits[0] 
       << c_bus_bits[1] 
       << c_bus_bits[2] 
       << c_bus_bits[3] 
       << c_bus_bits[4] 
       << c_bus_bits[5] 
       << c_bus_bits[6] 
       << c_bus_bits[7] 
       << endl;
  
  //create the individual phase pulses; these are summed to produce
  //the total pulse
  frac_pulse[0] = (c_bus == 0x87);
  frac_pulse[1] = (c_bus == 0xC3);
  frac_pulse[2] = (c_bus == 0xE1);
  frac_pulse[3] = (c_bus == 0xF0);
  frac_pulse[4] = (c_bus == 0x78);
  frac_pulse[5] = (c_bus == 0x3C);
  frac_pulse[6] = (c_bus == 0x1E);
  frac_pulse[7] = (c_bus == 0x0F);
  
  pulse.write(0);


  for(int ii=0; ii < 8; ii++){
    pulse.write(pulse.read() | (frac_pulse[ii] << ii));
  }
  
  
}

========================================================================================================================

When I run compile and run the simulation, only the test control module thread runs( m_test_control ) ( I traced this with gdb) and no other SC_THREADS or SC_METHODS from any other module gets called( or scheduled for execution.. The simulation ends when the thread from i_test_control exits... Can anyone help me figure out what's wrong with my code ???

Really appreciate the help !!! Raj

I have attached the tar ball for this code ...

Hi Guys

If I use wait(e1 | e2) in my thread(where e1 and e2 are sc_event), on the next line after this wait, is there a way to know whether it is an event on e1 or e2 which force the thread to come out of wait.

Thanks

RahulJn

Hi all,

Is their any availability of NAND FLASH model in SystemC like verilog ??

Thanks ,
Pruthvi

Dear all,

I'm implementing a custom channel which is basically an hybrid object, offering a fifo-lile interface on the reader side and a signal-like interface on the writer side. The code is given below (listing 1). Basically, it just wraps up a sc_signal so that it can be viewed as a never-empty FIFO on the reader side.

It works well except that the value changes -- that are correctly witnessed by issuing print msg in the write() method() -- are not dumped in the trace file (see listing 2).

My intuition is that the write actions are not viewed by the trace mechanism and that i should explicitly call a method for this in the write() method. 

But i can just figure out which one. I've browsed the ref man but cannot find the answer to this question : what events are exactly dumped in the trace file when a channel is registered as traced by calling sc_trace ?

Any clue ?

Jocelyn

template<class T>
class buffer_in
: public sc_signal_write_if<T>,
  public fifo_in_if<T>,
  public sc_prim_channel
{
protected:
  sc_signal<T> m_sig; 
  sc_event m_data_written_event;
public:
  explicit buffer_in( const char* name_ ) :
      m_sig(name_),
	  m_data_written_event((std::string(SC_KERNEL_EVENT_PREFIX)+"_write_event").c_str()) { }

  virtual ~buffer_in() { }

  // (read-only) fifo-conformant interface
  virtual int num_available() const { return 1; }
  virtual void read( T& t) { t = m_sig.read(); }
  virtual T read() { return  m_sig.read(); }
  virtual bool nb_read( T& t) { t = m_sig.read(); return true; }
  virtual const sc_event& data_written_event() const { return m_data_written_event; }
  virtual T peek() const { return m_sig.read(); }
  virtual bool rd_rdy() const { return 1; }

  // (write-only) signal-conformant interface
  virtual void write( const T& t) {
    cout << "*** *** buffer " << m_sig.name() << " : write: " << t << endl; cout.flush();
    m_data_written_event.notify(SC_ZERO_TIME); m_sig.write(t); };

  // other methods
  virtual const char* kind() const { return "buffer_in"; }
  operator T () { return read(); }
  void trace( sc_trace_file* tf ) const { m_sig.trace(tf); } // sc_trace( tf, m_sig.read(), name()); }
};

int sc_main(int argc, char* argv[]) {
  sc_clock clk("clk", 10, SC_NS, 1);
  sc_trace_file *trace_file;
  trace_file = sc_create_vcd_trace_file ("test_buffer");
  ...
  buffer_in<sc_uint<8> > w("b1");
  ...
  sc_trace(trace_file, clk, "clk");
  sc_trace(trace_file, w, "b1");
  sc_start(100, SC_NS);
  sc_close_vcd_trace_file (trace_file);
  cout << "Wrote file test_buffer.vcd" << endl;
  return EXIT_SUCCESS;
}

Hi ALl:

My working environment is visual studio 2010 express + cygwin64.

I followed the READNE_windows.txt in the systemc regression release and did following steps.

SystemC unziped at c:\systemc-2.3.0

the regression at: C:\systemc_regressions-2.3.0

1. Opened systemc 2.3.0 msvc80 project and compiled (debug mode).

2. Visual studio command prompt (2010)

    - c:\cygwin64\Cygwin.bat

    - export SYSTEMC_HOME=/cygdrive/c/systemc-2.3.0

    - export CXX=cl

    - make a "run" under /cygdrive/c/systemc_regressions-2.3.0

    - and do "../scripts/verify.pl -g systemc" under the run

3. the perl script runs well, and I can see the setting prints are fine, like SYSTEMC_ARCH, SYSTEMC_HOME, TLM_HOME....

4. All test failed and when I check the log, I got

    cl : Command line warning D9035 : option 'GZ' has been deprecated and will be removed in a future release
    cl : Command line warning D9036 : use 'RTC1' instead of 'GZ'
    async_reset.cpp
    Unknown compiler version - please run the configure tests and report the results
    LINK: extra operand ‘/NODEFAULTLIB:LIBCD’
    Try 'LINK --help' for more information.

Anyone have run the regression before and have any idea for the that?

One thing I can think of is that the default VS dir is MSVC80 for SystemC while I am using MSVC10, systemc lib link failed? While I tried to compy msvc80 and renamed it to msvc10, still not working

I'm working on a small simulation library based on SystemC for a research project.  What I'd like to do is have the I/O from a testbench module be dynamically determined at runtime (perhaps through some sort of configuration file).  The point is to avoid recompilation and have the testbench dynamically configure itself to accommodate the UUT.

The problem is not that I cannot traverse the hierarchy (I've figured that out) and get the ports.  The problem is that I cannot seem to dynamically generate a "database".  Since all the ports are templated, I can't generate a generic data structure for all ports.  For example, I'd like to be able to do something like:

std::unordered_map<const std::string, ????> dut_ports;

I don't know what to use for ????.  I've thought of using some sort of generic wrapper, e.g.:

struct port_wrapper

{

  template<T>

  port_wrapper(T port_)

    port(port_)

  {

  }

  T port;

};

But this is still a problem since T isn't known until runtime.

Is there a way to store a "generic" pointer to a sc_in, sc_out, or sc_inout?  Looking through the source code, it looks like everything is parameterized all the way back until sc_interface.  But sc_interface doesn't provide any methods to access the port (i.e. read/write).

Any hints or suggestions?

Hello guyz ,

i am getting this error on a particular notification

below is the stack

Program received signal SIGBUS, Bus error.
0x00007ffff7d0317e in sc_core::sc_event::notify(sc_core::sc_time const&) () from /usr/local/systemc-2.3.1/lib-linux64/libsystemc-2.3.1.so
(gdb) backtrace
#0  0x00007ffff7d0317e in sc_core::sc_event::notify(sc_core::sc_time const&) () from /usr/local/systemc-2.3.1/lib-linux64/libsystemc-2.3.1.so
#1  0x00000000004225c2 in logical_unit<unsigned int, 32u>::response (this=0x6f5220, task_comand=33 '!', rsponse=0 '\000', lun1=2 '\002', t_tag=17 '\021')
    at /home/mic-24/Desktop/qemu+other/ufs_dropbox_21/include/logical_unit.tpp:1314
#2  0x0000000000429d44 in logical_unit<unsigned int, 32u>::lu1_data_in (this=0x6f5220, current_cmd=..., opcode_current_cmd=8 '\b', lu_resent_data=0 '\000', 
    lun_ftl=1 '\001') at /home/mic-24/Desktop/qemu+other/ufs_dropbox_21/include/logical_unit.tpp:458
#3  0x0000000000424028 in logical_unit<unsigned int, 32u>::command_processing (this=0x6f5220, lu_resent_data=0 '\000', lun_ftl=1 '\001')
    at /home/mic-24/Desktop/qemu+other/ufs_dropbox_21/include/logical_unit.tpp:199
#4  0x000000000041bd22 in logical_unit<unsigned int, 32u>::logical_unit_thread (this=0x6f5220)
    at /home/mic-24/Desktop/qemu+other/ufs_dropbox_21/include/logical_unit.tpp:37
#5  0x0000000000416979 in device<unsigned int, 32u>::logical_unit_trans (this=0x6dce00) at /home/mic-24/Desktop/qemu+other/ufs_dropbox_21/include/device.tpp:315
#6  0x00007ffff7d1dde6 in sc_core::sc_thread_cor_fn(void*) () from /usr/local/systemc-2.3.1/lib-linux64/libsystemc-2.3.1.so
#7  0x00007ffff7d0248b in sc_core::sc_cor_pthread::invoke_module_method(void*) () from /usr/local/systemc-2.3.1/lib-linux64/libsystemc-2.3.1.so
#8  0x0000003362a079d1 in start_thread () from /lib64/libpthread.so.0
#9  0x00000033626e886d in clone () from /lib64/libc.so.6
(gdb) 

SC_THREAD(A)

SC_THREAD( B )

SC_THREAD( C )

A(){

       while(1){

                     wait(e_A);

                     e_B.notify(SC_ZERO_TIME);

                     e_C.notify(SC_ZERO_TIME);

                     -------

                    }

}

B(){

       while(1){

                     wait(e_B );

                     -------

                     -------

                    }

}

C(){

       while(1){

                     wait(e_C);

                     -------

                     -------

                    }

}

In the above case acc. to systemc scheduler the threads will be notified in delta phase.

Now my question is, whether its a nodeterminstic condition which of the thread will run 1st b or c , or is it like that the one notified 1st will get the control 1st.

Hi Everyone - I had been trying to install and run a simple helloworld program using systemc 2.3.1, windows 8 and Visual Studio 2013. The library itself compiles fine. However, When i write a simple hello world program and builds it, it gives error "sprintf is unsafe. use sprintf_s. To disable deprecation, use _CRT_SECURE_NO_WARNINGS". After disabling it in the options. It started giving me 100's of link errors. I checked with the INSTALL guide of systemc 2.3.1, it only says supported on windows 7. Could this be the problem?

Regards,

Mustafa

Hey Guys, I don't know if you know about GDB Pretty-Printer. Over the last week I tried to write a Pretty-Printer analyzing the SystemC implementation and learning how the information of the data is stored within the classes. This work is still not finished, because I have to write a test-interface to see if really all datatypes are working.

However, because it is just a freetime project and eventually I will not find the time in future to improve this Pretty-Printer I will show you the current status.

You can find the Pretty-Printer under following link: 

https://github.com/AHeimberger/SystemC-2.3-Pretty-Printer

An instruction about installing the Pretty-Printer can be found here:

http://aheimberger.bplaced.net/2014/11/systemc23-pretty-printer/

Hope this Pretty-Printer helps you and does not cause to many problems. I were also able to use them within Eclipse.

Cheers Andi

hai ...
 
                  i had been trying to install systemc 2.0 in red hat linux in my pc ...
                  i downloaded system c 2.0 file from accellera.
                  i found that it works with GNU compiler ,so i downloaded GNU c++ compiler 2.95.2 and run in linux...i found these message while approaching (error meniond as image below)

I followed these steps for installing GCC compiler...i creatd test file and run it in linux  mentiond in(8&9)...but i found missing something in first four points... i didnt figure out these points(1 to 4)....can anyone help me regarding these installation and my error in it?????????

insatallation steps found in (http://www.tldp.org/...FS-HOWTO-7.html)

1. Reboot the computer into the LFS system
2. Remount the LFS partition in read-write mode
3. Mount the partition that contains the gcc-2.95.2 and gcc-install directories
4. Create a symlink that links /usr/src/gcc-2.95.2 to the usr/src/gcc-2.95.2 directory that contains the gcc source files.
5. Go to the gcc-install directory
6. Install the package by running make install
7. Go to the /root directory
8. Compile+link test.c by running gcc test.c -o test
9. Compile+link test2.c by running g++ test2.c -o test2
10. Run both programs
11. If both programs run without errors or crashing than the compilers and linkers seem to be working
12. Remove the /usr/src/gcc-2.95.2 symlink

thanks and regards

R.KARTHIKEYAN

Hi,

Does ports like sc_in<> follow request-update thing?

For example,  If I write to a port sc_In  will it be updated immediately or after delta time(like in signals)? 

Hello,

I'm facing some porblems in using SystemC Verifcation Library, my codes just don't compile.

I'm using Ubuntu 14.04 (64 bits) and I followed the instructions on the INSTALL text file that comes with de SCV package.

I used: ../configure prefix=/usr/local/scv-2.0.0 with-systemc=/usr/local/systemc-2.3.1

(I've created the /usr/loca//scv-2.0.0 beforehand)

After the configuration: make & sudo make install

The installation finishes without errors.

The problems start when I try to use the library in codes. I add to my codes "#include<scv.h>" and add my makefiles looks like this:

CC = g++
INCDIR = -I. -I$(SYSTEMC)/include -I$(SCV)/include
LIBDIR = -L. -L$(SYSTEMC)/lib-linux64 -L$(SCV)/lib-linux64
LIBS   = -lsystemc -lscv -lm
CFLAGS = -O2 -Wall -DDEBUG_SYSTEMC

TARGET = verification.x
SRCS   = top.cpp
OBJS   = $(SRCS:.cpp=.o)

all: $(TARGET)

$(TARGET): $(OBJS)
    $(CC) -o $@ $(LIBDIR) $(LIBS) $(OBJS)

.cpp.o:
    $(CC) $(CFLAGS) $(INCDIR) -c $<

clean:
    @rm -f *.o $(TARGET)

Obs.: the environment variable SCV is previously set

Then when I run the make command I get the following (not the full output):

top.o:(.rodata._ZTV14scv_extensionsIcE[_ZTV14scv_extensionsIcE]+0x210): undefined reference to `_scv_extension_util::get_dynamic_data()'
top.o:(.rodata._ZTV14scv_extensionsIcE[_ZTV14scv_extensionsIcE]+0x218): undefined reference to `_scv_extension_rand_char::updated()'
top.o:(.rodata._ZTV14scv_extensionsIcE[_ZTV14scv_extensionsIcE]+0x220): undefined reference to `_scv_extension_rand_char::uninitialize()'
top.o:(.rodata._ZTV14scv_extensionsIcE[_ZTV14scv_extensionsIcE]+0x228): undefined reference to `_scv_extension_rand_char::initialize() const'
top.o:(.rodata._ZTV14scv_extensionsIcE[_ZTV14scv_extensionsIcE]+0x230): undefined reference to `_scv_extension_rand_char::is_initialized() const'
top.o:(.rodata._ZTV14scv_extensionsIcE[_ZTV14scv_extensionsIcE]+0x238): undefined reference to `_scv_extension_callbacks_char::remove_cb(int)'

top.o:(.rodata._ZTV14scv_extensionsIcE[_ZTV14scv_extensionsIcE]+0x260): undefined reference to `_scv_extension_rand_char::generate_value_()'
collect2: error: ld returned 1 exit status
make: *** [verification.x] Error 1

The error seems to come from a library linking problem, but to me it looks like the SCV libraries are linked correctly.

Does anyone knows what is going on?

Thanks in advance,

Eduardo.
 

Hi, 

I was trying to figure out how to run SystemC simulation in a main function.

I have read LRM 4.3.2, Function sc_elab_and_sim, but still can't get it.

This is what I did: 

int sc_elab_and_sim(int argc, char *argv[])

int main()

{

}

I use argc to decide which set of modules I want to run, just for test.

And I got an exception when it starting second sc_start:

libc++abi.dylib: terminating with uncaught exception of type sc_core::sc_report: Error: (E529) insert module failed: simulation running

Hi ,

Recently I have studied that SystemC can be used To model High level functional models to detailed clock cycle accurate RTL models.

If any company done like this then the they can save the time and energy too. Because at different levels we are using the same language.

But as of my knowledge many companies uses SystemC at system Modeling only.

Why they are not using the same language at RTL instead it has many advantages. ?

Please clear this doubt

Thanks,

Mani

Hello All,

I need some strong suggestion regarding modeling of TIMER.

I am new in systemc.

Want to know what are the things a best model should consist of and how its modeling should be done ?

Since timer has a clock time period,

should i model it in by incrementing/decrementing the counter and applying a delay for timer period 

or i should model it without any delay by using sensitivity to the new write in register and decremnting/ incrementing the counter value by evaluating the current time period and previous sensitivity time period by clock time period.

With Warm Regards.